However the dwarf emitter only understands a constant
register offset.
- The solution choosen here is to use the otherwise unused IP0
+ The solution chosen here is to use the otherwise unused IP0
as a temporary register to hold the current SP value. The
CFA is described using IP0 then SP is modified. */
func_type = arm_current_func_type ();
/* Naked functions don't have epilogue. Hence, generate return pattern, and
- let output_return_instruction take care of instruction emition if any. */
+ let output_return_instruction take care of instruction emission if any. */
if (IS_NAKED (func_type)
|| (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN))
{
gcc_assert (move[blocked].links != -1);
/* Replace src of blocking move with scratch reg. */
move[move[blocked].links].src = scratch;
- /* Make dependent on scratch move occuring. */
+ /* Make dependent on scratch move occurring. */
move[blocked].links = size;
size=size+1;
}
/* X86_TUNE_PAD_RETURNS */
m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC,
- /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
+ /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short function. */
m_ATOM,
/* X86_TUNE_EXT_80387_CONSTANTS */
/* Find the default version and make it the first node. */
first_v = node_v;
- /* Go to the beginnig of the chain. */
+ /* Go to the beginning of the chain. */
while (first_v->prev != NULL)
first_v = first_v->prev;
default_version_info = first_v;
}
}
-/* Fix up a Windows system unwinder issue. If an EH region falls thru into
+/* Fix up a Windows system unwinder issue. If an EH region falls through into
the epilogue, the Windows system unwinder will apply epilogue logic and
produce incorrect offsets. This can be avoided by adding a nop between
the last insn that can throw and the first insn of the epilogue. */
if (insn == NULL)
continue;
- /* We only care about preceeding insns that can throw. */
+ /* We only care about preceding insns that can throw. */
insn = prev_active_insn (insn);
if (insn == NULL || !can_throw_internal (insn))
continue;
op0 = gen_reg_rtx (mode);
emit_move_insn (op0, gen_lowpart (mode, op1));
- /* Load even elements into the second positon. */
+ /* Load even elements into the second position. */
emit_insn (gen_load_even (op0,
force_reg (inner_mode,
ops [i + i + 1]),
/* Helper function of ix86_expand_mul_widen_evenodd. Return true
if op is CONST_VECTOR with all odd elements equal to their
- preceeding element. */
+ preceding element. */
static bool
const_vector_equal_evenodd_p (rtx op)
/* Save the link registers. We could try to save just one register
here. This would reduce the amount of stack space required.
- There hasnt been a good reason to do that so far. */
+ There hasn't been a good reason to do that so far. */
if (!picochip_can_eliminate_link_sp_save ())
picochip_emit_save_register (gen_rtx_REG (SImode, LINK_REGNUM),
special_save_offset);
}
/* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
- should be 4 byte aligned. We can currently guarentee that only if the base
+ should be 4 byte aligned. We can currently guarantee that only if the base
address is FP(R13) and the offset is aligned. */
if (reg1 == reg2 && reg1 == 13 && abs(offset1-offset2) == 2 && minimum(offset1, offset2) % 4 == 0)
LDL r[3:2],[r11]
NOTE:
- 1. The LDWs themselves only guarentee that r11 will be a 2-byte
+ 1. The LDWs themselves only guarantee that r11 will be a 2-byte
aligned address. Only FP can be assumed to be 4 byte aligned.
2. The progression of addresses and the register numbers should
be similar. For eg., if you swap r2 and r3 in the above instructions,
if (GET_MODE (insn) == TImode || !picochip_schedule_type == DFA_TYPE_SPEED)
picochip_reset_vliw (insn);
- /* No VLIW scheduling occured, so don't go any further. */
+ /* No VLIW scheduling occurred, so don't go any further. */
if (picochip_schedule_type != DFA_TYPE_SPEED)
return;
#define FUNCTION_BOUNDARY 8
/* This is the biggest alignment that can be allowed on this machine.
- Since the STANs have only 256 byte memory, it doesnt make sense
+ Since the STANs have only 256 byte memory, it doesn't make sense
to have alignments greater than 32 bytes. Hence the value */
#define MAX_OFILE_ALIGNMENT 32*8
encoding.
Also r12 is put towards the end for leaf functions. Since leaf functions
do not have any calls, the prologue/epilogue for them wouldnt save up/
- restore its value. So, it doesnt make sense for us to use it in the middle,
+ restore its value. So, it doesn't make sense for us to use it in the middle,
if we can avoid it. */
#define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
#define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
/* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
on traditional floating point registers, and the VMRGOW/VMRGEW instructions
only work on the traditional altivec registers, note if an altivec register
- was choosen. */
+ was chosen. */
static enum rs6000_reg_type
register_to_reg_type (rtx reg, bool *is_altivec)
rx_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
const_tree type ATTRIBUTE_UNUSED)
{
- /* Older versions of the RX backend aligned all on-stack arguements
+ /* Older versions of the RX backend aligned all on-stack arguments
to 32-bits. The RX C ABI however says that they should be
aligned to their natural alignment. (See section 5.2.2 of the ABI). */
if (TARGET_GCC_ABI)
/* These intrinsics are being made available for compatibility with
the IBM XL compiler. For documentation please see the "z/OS XL
- C/C++ Programming Guide" publically available on the web. */
+ C/C++ Programming Guide" publicly available on the web. */
extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__TM_simple_begin ()
}
/* This function is called via hook TARGET_SCHED_REORDER before
- issueing one insn from list READY which contains *NREADYP entries.
+ issuing one insn from list READY which contains *NREADYP entries.
For target z10 it reorders load instructions to avoid early load
conflicts in the floating point pipeline */
static int
projects / thirdparty / gcc.git / commitdiff
