--- /dev/null
+From sumit.semwal@linaro.org Tue Oct 8 12:17:06 2024
+From: Sumit Semwal <sumit.semwal@linaro.org>
+Date: Thu, 3 Oct 2024 20:05:32 +0530
+Subject: Revert "arm64: dts: qcom: sm8250: switch UFS QMP PHY to new style of bindings"
+To: stable@vger.kernel.org
+Cc: dmitry.baryshkov@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Sumit Semwal <sumit.semwal@linaro.org>
+Message-ID: <20241003143532.108444-1-sumit.semwal@linaro.org>
+
+From: Sumit Semwal <sumit.semwal@linaro.org>
+
+This reverts commit cf9c7b34b90b622254b236a9a43737b6059a1c14.
+
+This commit breaks UFS on RB5 in the 6.1 LTS kernels. The original patch
+author suggests that this is not a stable kernel patch, hence reverting
+it.
+
+This was reported during testing with 6.1.103 / 5.15.165 LTS kernels
+merged in the respective Android Common Kernel branches.
+
+Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++++------
+ 1 file changed, 14 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
+@@ -1702,7 +1702,7 @@
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+- phys = <&ufs_mem_phy>;
++ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+@@ -1746,8 +1746,10 @@
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm8250-qmp-ufs-phy";
+- reg = <0 0x01d87000 0 0x1000>;
+-
++ reg = <0 0x01d87000 0 0x1c0>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+@@ -1755,12 +1757,18 @@
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
++ status = "disabled";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+- #phy-cells = <0>;
+-
+- status = "disabled";
++ ufs_mem_phy_lanes: phy@1d87400 {
++ reg = <0 0x01d87400 0 0x16c>,
++ <0 0x01d87600 0 0x200>,
++ <0 0x01d87c00 0 0x200>,
++ <0 0x01d87800 0 0x16c>,
++ <0 0x01d87a00 0 0x200>;
++ #phy-cells = <0>;
++ };
+ };
+
+ ipa_virt: interconnect@1e00000 {