arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model

The FVP Rev C model includes CoreSight ETE and TRBE support. These
features can be enabled by specifying parameters when launching the
model:

  |  -C cluster0.has_ete: 1
  |  -C cluster1.has_ete: 1
  |  -C cluster0.has_trbe: 1
  |  -C cluster1.has_trbe: 1

This change adds device tree nodes for the ETE and TRBE. They are
disabled by default to prevent kernel warnings from failed driver
probes, as the model does not enable the features unless explicitly
specified as mentioned above.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Message-Id: <20250512151149.13111-1-leo.yan@arm.com>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index a5024075e3f330330ab384684d31052e034b3947..68a69f17e93d80d5de2204b172867b3542a28931 100644 (file)
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -272,6 +272,60 @@
                interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       ete-0 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu0>;
+               status = "disabled";
+       };
+
+       ete-1 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu1>;
+               status = "disabled";
+       };
+
+       ete-2 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu2>;
+               status = "disabled";
+       };
+
+       ete-3 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu3>;
+               status = "disabled";
+       };
+
+       ete-4 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu4>;
+               status = "disabled";
+       };
+
+       ete-5 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu5>;
+               status = "disabled";
+       };
+
+       ete-6 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu6>;
+               status = "disabled";
+       };
+
+       ete-7 {
+               compatible = "arm,embedded-trace-extension";
+               cpu = <&cpu7>;
+               status = "disabled";
+       };
+
+       trbe {
+               compatible = "arm,trace-buffer-extension";
+               interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_LOW>;
+               status = "disabled";
+       };
+
        pci: pci@40000000 {
                #address-cells = <0x3>;
                #size-cells = <0x2>;