aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads and stores to be ABI compliant.

2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads
	and stores to be ABI compliant.

From-SVN: r205266

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 15459d3e30728cb5a68a4f09e8f02be86d55b83d..835030e4cb5f0da94fd26ba10fe73129f7540569 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads
+       and stores to be ABI compliant.
+
 2013-11-22  David Malcolm  <dmalcolm@redhat.com>
 
        * input.h (input_line): Remove.

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b9ebdf54431fcdaac6161a774bfe4d38fb52a44b..19ef2030bb014f47dd0477c3cc889a6f16fb8301 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -85,17 +85,17 @@
 
 (define_insn "*aarch64_simd_mov<mode>"
   [(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand"
-               "=w, Utv,  w, ?r, ?w, ?r, w")
+               "=w, m,  w, ?r, ?w, ?r, w")
        (match_operand:VD 1 "aarch64_simd_general_operand"
-               "Utv,  w,  w,  w,  r,  r, Dn"))]
+               "m,  w,  w,  w,  r,  r, Dn"))]
   "TARGET_SIMD
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
 {
    switch (which_alternative)
      {
-     case 0: return "ld1\t{%0.<Vtype>}, %1";
-     case 1: return "st1\t{%1.<Vtype>}, %0";
+     case 0: return "ldr\\t%d0, %1";
+     case 1: return "str\\t%d1, %0";
      case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>";
      case 3: return "umov\t%0, %1.d[0]";
      case 4: return "ins\t%0.d[0], %1";
@@ -113,9 +113,9 @@
 
 (define_insn "*aarch64_simd_mov<mode>"
   [(set (match_operand:VQ 0 "aarch64_simd_nonimmediate_operand"
-               "=w, Utv,  w, ?r, ?w, ?r, w")
+               "=w, m,  w, ?r, ?w, ?r, w")
        (match_operand:VQ 1 "aarch64_simd_general_operand"
-               "Utv,  w,  w,  w,  r,  r, Dn"))]
+               "m,  w,  w,  w,  r,  r, Dn"))]
   "TARGET_SIMD
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
@@ -123,9 +123,9 @@
   switch (which_alternative)
     {
     case 0:
-       return "ld1\t{%0.<Vtype>}, %1";
+       return "ldr\\t%q0, %1";
     case 1:
-       return "st1\t{%1.<Vtype>}, %0";
+       return "str\\t%q1, %0";
     case 2:
        return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>";
     case 3: