drivers: ddr: altera: Correct DDR calibration status check

Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index f8fc92060db6719256c5111f5b208cf7cb1cc4f1..2d0093c591c28533660e3ee683bcc8119e5df5af 100644 (file)
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat)
        debug("DDR: Triggerring emif reset\n");
        hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 
-       /* if seq2core[3] = 0, we are good */
+       /* if seq2core[2:0] = 0b0000_0111, we are good */
        ret = wait_for_bit_le32((const void *)(plat->hmc +
                                 RSTHANDSHAKESTAT),
-                                DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-                                false, 1000, false);
+                                DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK,
+                                true, 1000, false);
        if (ret) {
                printf("DDR: failed to get ack from EMIF\n");
                return ret;

diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 6031cef560e30c79e1e644929468db7b51a00291..6fe0653922ce03b0d3aae11207eb562ac470df2f 100644 (file)
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -77,7 +77,7 @@ struct altera_sdram_plat {
 #define DDR_HMC_INTMODE_INTMODE_SET_MSK                BIT(0)
 #define DDR_HMC_RSTHANDSHAKE_MASK              0x0000000f
 #define DDR_HMC_CORE2SEQ_INT_REQ               0x0000000f
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK         BIT(3)
+#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK      GENMASK(2, 0)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK                0x001f1f1f
 
 #define        DDR_HMC_ERRINTEN_INTMASK                                \