arm: dts: socfpga: remove "clk-phase" in sdmmc_clk

Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't
need the clk-phase in the sdmmc_clk anymore.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 57a5d6c924b113cd85a225b48e56a40530afd572..1d4a42cef48354ee6585c44764fdfc0b2eec95d8 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -453,7 +453,6 @@
                                                compatible = "altr,socfpga-gate-clk";
                                                clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
                                                clk-gate = <0xa0 8>;
-                                               clk-phase = <0 135>;
                                        };
 
                                        sdmmc_clk_divided: sdmmc_clk_divided {

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a06211fcb5c3a236f1fcb7fc3145161fb755491c..cc7d4a62dde79a8eb99f643e5ba661850d86c53a 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -365,7 +365,6 @@
                                                compatible = "altr,socfpga-a10-gate-clk";
                                                clocks = <&sdmmc_free_clk>;
                                                clk-gate = <0xC8 5>;
-                                               clk-phase = <0 135>;
                                        };
 
                                        qspi_clk: qspi_clk {