drm/i915: Simplify combo PLL frac w/a

We are applying the combo PLL frac w/a to all TGL+ platforms, except
RKL. I *think* all RKL machines use a 24 MHz refclk (certainly all
machines in our CI do) and so technically never need the adjustment.
But let's assume the hardware is exactly the same anyway and simplify
the code by applying the w/a to all TGL+ platforms.

v2: Keep the 38.4 MHz check

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250402171720.9350-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 76ab55ee4b80a28a11e8e426effc430797092038..84df41086a892e1850ac3d7dd51ef5df4b3e3905 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2604,11 +2604,8 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
 {
        return ((display->platform.elkhartlake &&
                 IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
-                display->platform.dg1 ||
-                display->platform.tigerlake ||
-                display->platform.alderlake_s ||
-                display->platform.alderlake_p) &&
-                display->dpll.ref_clks.nssc == 38400;
+               DISPLAY_VER(display) >= 12) &&
+               display->dpll.ref_clks.nssc == 38400;
 }
 
 struct icl_combo_pll_params {