riscv: dts: th1520: Add DRAM controller

Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index b34ac323503af2f5313bf7faef76fded17aac5a8..4a523f8048bfd397f5080f49aa133043eb59da50 100644 (file)
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -371,6 +371,16 @@
                        status = "disabled";
                };
 
+               ddrc: ddrc@fffd000000 {
+                       compatible = "thead,th1520-ddrc";
+                       reg = <0xff 0xfd000000 0x0 0x1000000>,
+                             <0xff 0xfe000000 0x0 0x1000000>,
+                             <0xff 0xff000000 0x0 0x4000>,
+                             <0xff 0xff005000 0x0 0x1000>;
+                       reg-names = "phy-0", "phy-1", "ctrl", "sys";
+                       bootph-pre-ram;
+               };
+
                timer4: timer@ffffc33000 {
                        compatible = "snps,dw-apb-timer";
                        reg = <0xff 0xffc33000 0x0 0x14>;