/* GRF_GPIO4C_IOMUX */
GRF_GPIO4C0_SEL_SHIFT = 0,
GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
- GRF_UART2DGBB_SIN = 2,
+ GRF_UART2DBGB_SIN = 2,
GRF_HDMII2C_SCL = 3,
GRF_GPIO4C1_SEL_SHIFT = 2,
GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
- GRF_UART2DGBB_SOUT = 2,
+ GRF_UART2DBGB_SOUT = 2,
GRF_HDMII2C_SDA = 3,
GRF_GPIO4C2_SEL_SHIFT = 4,
GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
GRF_PWM_0 = 1,
GRF_GPIO4C3_SEL_SHIFT = 6,
GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
- GRF_UART2DGBC_SIN = 1,
+ GRF_UART2DBGC_SIN = 1,
GRF_GPIO4C4_SEL_SHIFT = 8,
GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
GRF_UART2DBGC_SOUT = 1,
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+ GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);