clk: renesas: rzg2l: Simplify SAM PLL configuration macro

Replace the PLL146_CONF() macro and its associated CPG_SAMPLL_CLK{1,2}(n)
helpers with a single CPG_SAM_PLL_CONF(stby) macro that takes the PLL
standby register offset directly.

This removes the implicit coupling between PLL index n and register layout
and eliminates the now-redundant GET_REG_SAMPLL_CLK2() macro. The RZ/V2M
PLL4 definition is also updated to use the new macro with its explicit
standby offset (0x100), removing the local PLL4_CONF define.

No functional changes.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260519141518.389670-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 70944ef8c5b863aeac201d0bfc32ebcbd619ce3b..59d6ee2e888fa70612ac4ce40bdaf9f1c2477295 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -103,7 +103,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
        /* Internal Core Clocks */
        DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
        DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
-       DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
+       DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_SAM_PLL_CONF(0)),
        DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
        DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
        DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 2d3487203bf541b81c4c8801f3525acabc16aba8..913cca6dd46fc52ceb329a786bc4af4a86217ca5 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -159,7 +159,7 @@ static const struct {
                /* Internal Core Clocks */
                DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
                DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
-               DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
+               DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_SAM_PLL_CONF(0)),
                DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
                DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
                DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),

diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index ba25429c244d6ea633bebab7d3ebce07c55e5a88..a99ab1375f07ca49f7892082b7327b6c8ca9c442 100644 (file)
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -16,11 +16,6 @@
 
 #include "rzg2l-cpg.h"
 
-#define RZV2M_SAMPLL4_CLK1     0x104
-#define RZV2M_SAMPLL4_CLK2     0x108
-
-#define PLL4_CONF      (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
-
 #define DIV_A          DDIV_PACK(0x200, 0, 3)
 #define DIV_B          DDIV_PACK(0x204, 0, 2)
 #define DIV_D          DDIV_PACK(0x204, 4, 2)
@@ -131,7 +126,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
        DEF_FIXED(".pll2_400",  CLK_PLL2_400,   CLK_PLL2_800,   1,      2),
        DEF_FIXED(".pll2_200",  CLK_PLL2_200,   CLK_PLL2_800,   1,      4),
        DEF_FIXED(".pll2_100",  CLK_PLL2_100,   CLK_PLL2_800,   1,      8),
-       DEF_SAMPLL(".pll4",     CLK_PLL4,       CLK_MAIN_2,     PLL4_CONF),
+       DEF_SAMPLL(".pll4",     CLK_PLL4,       CLK_MAIN_2,     CPG_SAM_PLL_CONF(0x100)),
 
        DEF_DIV_RO(".diva",     CLK_DIV_A,      CLK_PLL1,       DIV_A,  dtable_diva),
        DEF_DIV_RO(".divb",     CLK_DIV_B,      CLK_PLL2_400,   DIV_B,  dtable_divb),

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 426e93dc7a9891bf155673117105682bacab23b1..ad9aab2ecc624703436dc9d005384e2a82fbec4a 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -58,6 +58,10 @@
 #define RZG3S_DIV_NF           GENMASK(12, 1)
 #define RZG3S_SEL_PLL          BIT(0)
 
+#define CPG_PLL_STBY_OFFSET(conf)      FIELD_GET(GENMASK(23, 12), (conf))
+#define CPG_PLL_CLK1_OFFSET(x)         (CPG_PLL_STBY_OFFSET(x) + 0x4)
+#define CPG_PLL_CLK2_OFFSET(x)         (CPG_PLL_STBY_OFFSET(x) + 0x8)
+
 #define RZG3L_PLL_STBY_OFFSET(x)       (GET_REG_SAMPLL_CLK1(x) - 0x4)
 #define RZG3L_PLL_STBY_RESETB          BIT(0)
 #define RZG3L_PLL_STBY_RESETB_WEN      BIT(16)
@@ -72,7 +76,6 @@
 
 #define GET_REG_OFFSET(val)            ((val >> 20) & 0xfff)
 #define GET_REG_SAMPLL_CLK1(val)       ((val >> 22) & 0xfff)
-#define GET_REG_SAMPLL_CLK2(val)       ((val >> 12) & 0xfff)
 #define GET_REG_SAMPLL_SETTING(val)    ((val) & 0xfff)
 
 #define CPG_WEN_BIT            BIT(16)
@@ -1093,8 +1096,8 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
        if (pll_clk->type != CLK_TYPE_SAM_PLL)
                return parent_rate;
 
-       val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
-       val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
+       val1 = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf));
+       val2 = readl(priv->base + CPG_PLL_CLK2_OFFSET(pll_clk->conf));
 
        rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),
                               16 + SDIV(val2));

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 33f54ba0e64ee628dd97e396ab48fd72d3c717df..17ec6f285c21d09d970c50b1da00a9b2d43b12ba 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -58,11 +58,7 @@
 #define CPG_CLKSTATUS_SELSDHI0_STS     BIT(28)
 #define CPG_CLKSTATUS_SELSDHI1_STS     BIT(29)
 
-/* n = 0/1/2 for PLL1/4/6 */
-#define CPG_SAMPLL_CLK1(n)     (0x04 + (16 * n))
-#define CPG_SAMPLL_CLK2(n)     (0x08 + (16 * n))
-
-#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
+#define CPG_SAM_PLL_CONF(stby)         ((stby) << 12)
 
 #define DDIV_PACK(offset, bitpos, size) \
                (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))