drm/amdgpu/gfx12.1: replace BUG_ON() with WARN_ON()

There's no need to crash the kernel for these cases.

Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit e4d99e04b2e9b13b97d3b17804c735f62689db23)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 61c3577f829fe29cfe3f3f2e8e1a5438f88b9f5f..02c9cda186eed006ce3d38c7d1e2b1862738a707 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -248,7 +248,7 @@ static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
                           PACKET3_WAIT_REG_MEM__FUNCTION(3)));  /* equal */
 
        if (mem_space)
-               BUG_ON(addr0 & 0x3); /* Dword align */
+               WARN_ON(addr0 & 0x3); /* Dword align */
        amdgpu_ring_write(ring, addr0);
        amdgpu_ring_write(ring, addr1);
        amdgpu_ring_write(ring, ref);
@@ -3433,7 +3433,7 @@ static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring,
        }
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-       BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
+       WARN_ON(ib->gpu_addr & 0x3); /* Dword align */
        amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
                                (2 << 0) |
@@ -3466,9 +3466,9 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
         * aligned if only send 32bit data low (discard data high)
         */
        if (write64bit)
-               BUG_ON(addr & 0x7);
+               WARN_ON(addr & 0x7);
        else
-               BUG_ON(addr & 0x3);
+               WARN_ON(addr & 0x3);
        amdgpu_ring_write(ring, lower_32_bits(addr));
        amdgpu_ring_write(ring, upper_32_bits(addr));
        amdgpu_ring_write(ring, lower_32_bits(seq));
@@ -3515,9 +3515,6 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
 {
        struct amdgpu_device *adev = ring->adev;
 
-       /* we only allocate 32bit for each seq wb address */
-       BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
-
        /* write fence seq to the "addr" */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1)));