arch/powerpc: Remove unused function icp_native_cause_ipi_rm()

Remove icp_native_cause_ipi_rm() as it has no callers since
commit 53af3ba2e819("KVM: PPC: Book3S HV: Allow guest exit path to have
MMU on")

Signed-off-by: Gautam Menghani <gautam@linux.ibm.com>
Reviewed-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20250101134251.436679-1-gautam@linux.ibm.com

diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
index 89090485bec18f4e29f1f668ce8fdaae40728a44..60ef312dab059b8160f69930c4796ddf9c143e0b 100644 (file)
--- a/arch/powerpc/include/asm/xics.h
+++ b/arch/powerpc/include/asm/xics.h
@@ -31,7 +31,6 @@
 #ifdef CONFIG_PPC_ICP_NATIVE
 extern int icp_native_init(void);
 extern void icp_native_flush_interrupt(void);
-extern void icp_native_cause_ipi_rm(int cpu);
 #else
 static inline int icp_native_init(void) { return -ENODEV; }
 #endif

diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
index 700b67476a7d8dd6a48d866442ef7ec38773ba2e..4e89158a577cde5da12b5b14d162f60f480c6eff 100644 (file)
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -145,27 +145,6 @@ static void icp_native_cause_ipi(int cpu)
        icp_native_set_qirr(cpu, IPI_PRIORITY);
 }
 
-#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
-void icp_native_cause_ipi_rm(int cpu)
-{
-       /*
-        * Currently not used to send IPIs to another CPU
-        * on the same core. Only caller is KVM real mode.
-        * Need the physical address of the XICS to be
-        * previously saved in kvm_hstate in the paca.
-        */
-       void __iomem *xics_phys;
-
-       /*
-        * Just like the cause_ipi functions, it is required to
-        * include a full barrier before causing the IPI.
-        */
-       xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys;
-       mb();
-       __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR);
-}
-#endif
-
 /*
  * Called when an interrupt is received on an off-line CPU to
  * clear the interrupt, so that the CPU can go back to nap mode.