Merge branch 'next_pinctrl_sync' of https://source.denx.de/u-boot/custodians/u-boot-sh

- pinctrl re-sync for Renesas chips

diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi
index 8166e3c1ff4e58f6c6c3e4c83f3fd6ca7bbc2ea8..2e9927b97732dc36c9d24c58ec5ecb726aa503f4 100644 (file)
--- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
+++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
@@ -367,7 +367,7 @@
 
                assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
                                  <&versaclock6_bb 3>, <&versaclock6_bb 4>;
-               assigned-clock-rates = <24000000>, <24000000>, <24000000>,
+               assigned-clock-rates = <24000000>, <24000000>, <24576000>,
                                       <24576000>;
 
                OUT1 {
@@ -437,20 +437,6 @@
                };
        };
 
-       /* 0 - lcd_reset */
-       /* 1 - lcd_pwr */
-       /* 2 - lcd_select */
-       /* 3 - backlight-enable */
-       /* 4 - Touch_shdwn */
-       /* 5 - LCD_H_pol */
-       /* 6 - lcd_V_pol */
-       gpio_exp1: gpio@20 {
-               compatible = "onnn,pca9654";
-               reg = <0x20>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
        touchscreen@26 {
                compatible = "ilitek,ili2117";
                reg = <0x26>;
@@ -482,6 +468,16 @@
                        };
                };
        };
+
+       gpio_exp1: gpio@70 {
+               compatible = "nxp,pca9538";
+               reg = <0x70>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
+                                 "backlight-enable", "Touch_shdwn",
+                                 "LCD_H_pol", "lcd_V_pol";
+       };
 };
 
 &lvds0 {
@@ -638,6 +634,25 @@
        #clock-cells = <1>;
        clock-frequency = <11289600>;
 
+       /* Reference versaclock instead of audio_clk_a */
+       clocks = <&cpg CPG_MOD 1005>,
+                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                <&versaclock6_bb 4>, <&audio_clk_b>,
+                <&audio_clk_c>,
+                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+
        status = "okay";
 
        ports {

diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi
index d3fc8ffd5b4c1a2e53cf0f07452eae09ff519a76..68b04e56ae56232eebf6cd8746f08f97060c88f5 100644 (file)
--- a/arch/arm/dts/beacon-renesom-som.dtsi
+++ b/arch/arm/dts/beacon-renesom-som.dtsi
@@ -59,7 +59,7 @@
        status = "okay";
 
        phy0: ethernet-phy@0 {
-               compatible = "ethernet-phy-id004d.d074",
+               compatible = "ethernet-phy-id0022.1640",
                             "ethernet-phy-ieee802.3-c22";
                reg = <0>;
                interrupt-parent = <&gpio2>;

diff --git a/arch/arm/dts/condor-common.dtsi b/arch/arm/dts/condor-common.dtsi
index dfbe35bf46e00c72fef4baddab9ccaeb6bcb4dac..7c34d14dcd7e1ca0d4007059c230c0542357fce8 100644 (file)
--- a/arch/arm/dts/condor-common.dtsi
+++ b/arch/arm/dts/condor-common.dtsi
@@ -21,6 +21,7 @@
 
        chosen {
                stdout-path = "serial0:115200n8";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
        };
 
        d1_8v: regulator-2 {

diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
index b1eb6a08029a58a0bfec985f918132350ef225aa..83104af2813eb4a08323eda9eb44fdc5fc981448 100644 (file)
--- a/arch/arm/dts/hihope-common.dtsi
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -3,15 +3,26 @@
  * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
  * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
  *
- * Copyright (C) 2021 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
  */
 
 #include <dt-bindings/gpio/gpio.h>
 
 / {
        aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+               i2c7 = &iic_pmic;
                serial0 = &scif2;
                serial1 = &hscif0;
+               mmc0 = &sdhi3;
+               mmc1 = &sdhi0;
+               mmc2 = &sdhi2;
        };
 
        chosen {
@@ -50,7 +61,7 @@
                };
        };
 
-       reg_1p8v: regulator0 {
+       reg_1p8v: regulator-1p8v {
                compatible = "regulator-fixed";
                regulator-name = "fixed-1.8V";
                regulator-min-microvolt = <1800000>;
@@ -59,7 +70,7 @@
                regulator-always-on;
        };
 
-       reg_3p3v: regulator1 {
+       reg_3p3v: regulator-3p3v {
                compatible = "regulator-fixed";
                regulator-name = "fixed-3.3V";
                regulator-min-microvolt = <3300000>;
@@ -137,7 +148,7 @@
 };
 
 &gpio6 {
-       usb1-reset {
+       usb1-reset-hog {
                gpio-hog;
                gpios = <10 GPIO_ACTIVE_LOW>;
                output-low;
@@ -328,6 +339,8 @@
        vqmmc-supply = <&reg_1p8v>;
        bus-width = <8>;
        mmc-hs200-1_8v;
+       no-sd;
+       no-sdio;
        non-removable;
        fixed-emmc-driver-type = <1>;
        status = "okay";

diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts
index 70d034c26dd08ace43c101fc8dbca10a358f2e85..105f9c71f9fd54f4ba3ecfc9cb58d98d60303450 100644 (file)
--- a/arch/arm/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -41,6 +41,9 @@
                bank-width = <4>;
                device-width = <1>;
 
+               clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
+               power-domains = <&cpg_clocks>;
+
                #address-cells = <1>;
                #size-cells = <1>;
 

diff --git a/arch/arm/dts/r7s72100.dtsi b/arch/arm/dts/r7s72100.dtsi
index 2211f88ede2ad351fdbbd1c2e07865a3448f8a97..b07b71307f24ad592183bdff75bd20622cf7ced8 100644 (file)
--- a/arch/arm/dts/r7s72100.dtsi
+++ b/arch/arm/dts/r7s72100.dtsi
@@ -313,9 +313,9 @@
                mmcif: mmc@e804c800 {
                        compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
                        reg = <0xe804c800 0x80>;
-                       interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
                        power-domains = <&cpg_clocks>;
                        reg-io-width = <4>;
@@ -323,12 +323,12 @@
                        status = "disabled";
                };
 
-               sdhi0: sd@e804e000 {
+               sdhi0: mmc@e804e000 {
                        compatible = "renesas,sdhi-r7s72100";
                        reg = <0xe804e000 0x100>;
-                       interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 
                        clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
                                 <&mstp12_clks R7S72100_CLK_SDHI01>;
@@ -339,12 +339,12 @@
                        status = "disabled";
                };
 
-               sdhi1: sd@e804e800 {
+               sdhi1: mmc@e804e800 {
                        compatible = "renesas,sdhi-r7s72100";
                        reg = <0xe804e800 0x100>;
-                       interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
-                                     GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 
                        clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
                                 <&mstp12_clks R7S72100_CLK_SDHI11>;
@@ -467,11 +467,12 @@
                        #clock-cells = <1>;
                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0xfcfe0438 4>;
-                       clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+                       clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
                        clock-indices = <
                                R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+                               R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
                        >;
-                       clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+                       clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
                };
 
                mstp10_clks: mstp10_clks@fcfe043c {
@@ -498,7 +499,7 @@
                        clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
                };
 
-               pinctrl: pin-controller@fcfe3000 {
+               pinctrl: pinctrl@fcfe3000 {
                        compatible = "renesas,r7s72100-ports";
 
                        reg = <0xfcfe3000 0x4230>;
@@ -607,6 +608,8 @@
                                     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "tei", "ri", "ti", "spi", "sti",
+                                         "naki", "ali", "tmoi";
                        clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
                        clock-frequency = <100000>;
                        power-domains = <&cpg_clocks>;
@@ -626,6 +629,8 @@
                                     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "tei", "ri", "ti", "spi", "sti",
+                                         "naki", "ali", "tmoi";
                        clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
                        clock-frequency = <100000>;
                        power-domains = <&cpg_clocks>;
@@ -645,6 +650,8 @@
                                     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "tei", "ri", "ti", "spi", "sti",
+                                         "naki", "ali", "tmoi";
                        clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
                        clock-frequency = <100000>;
                        power-domains = <&cpg_clocks>;
@@ -664,12 +671,33 @@
                                     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "tei", "ri", "ti", "spi", "sti",
+                                         "naki", "ali", "tmoi";
                        clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
                        clock-frequency = <100000>;
                        power-domains = <&cpg_clocks>;
                        status = "disabled";
                };
 
+               irqc: interrupt-controller@fcfef800 {
+                       compatible = "renesas,r7s72100-irqc",
+                                    "renesas,rza1-irqc";
+                       #interrupt-cells = <2>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0xfcfef800 0x6>;
+                       interrupt-map =
+                               <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                               <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                               <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                               <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                               <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                               <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                               <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                               <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-map-mask = <7 0>;
+               };
+
                mtu2: timer@fcff0000 {
                        compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
                        reg = <0xfcff0000 0x400>;

diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
index 9ae67263c0df3fed712aa6f79247be1be2a4125c..24da6ee6eccd3f9a861b8d6601fa948e6fceb7b7 100644 (file)
--- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
@@ -58,24 +58,3 @@
        clock-names = "du.0", "du.1", "du.2",
                      "dclkin.0", "dclkin.1", "dclkin.2";
 };
-
-/* Reference versaclock instead of audio_clk_a */
-&rcar_sound {
-       clocks = <&cpg CPG_MOD 1005>,
-                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                <&versaclock6_bb 4>, <&audio_clk_b>,
-                <&audio_clk_c>,
-                <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
-};

diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi
index cddffe876453ce6c47dd6fe479a57475b4000548..38f5bfe85fca497e10d4071f4002c39f55466e8e 100644 (file)
--- a/arch/arm/dts/r8a774a1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774a1-u-boot.dtsi
@@ -28,7 +28,6 @@
 /delete-node/ &hdmi0;
 /delete-node/ &lvds0;
 /delete-node/ &rcar_sound;
-/delete-node/ &sdhi2;
 /delete-node/ &sound_card;
 /delete-node/ &vin0;
 /delete-node/ &vin1;

diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi
index 7e643243c3be6e89ef7f7afa4182429fc36b194b..9065dc243428f128bc65c4b4ce3d6f8d976d9973 100644 (file)
--- a/arch/arm/dts/r8a774a1.dtsi
+++ b/arch/arm/dts/r8a774a1.dtsi
@@ -1678,7 +1678,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2359,8 +2359,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2371,6 +2371,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 
@@ -2386,8 +2388,8 @@
                                 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
                                 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
                                 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2398,6 +2400,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 318>;
+                       iommu-map = <0 &ipmmu_hc 1 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
index 89d708346ba8176dc5799d0c2aed4d081853da2f..8b9df6afffde71cb94fa7b54e5a7c9ee46a03ae9 100644 (file)
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
@@ -14,6 +14,14 @@
        compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
 
        aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+               i2c7 = &iic_pmic;
                serial0 = &scif2;
                serial1 = &hscif0;
                serial2 = &hscif1;
@@ -46,24 +54,3 @@
        clock-names = "du.0", "du.1", "du.3",
                "dclkin.0", "dclkin.1", "dclkin.3";
 };
-
-/* Reference versaclock instead of audio_clk_a */
-&rcar_sound {
-       clocks = <&cpg CPG_MOD 1005>,
-                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                <&versaclock6_bb 4>, <&audio_clk_b>,
-                <&audio_clk_c>,
-                <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
-};

diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi
index 3b34f82160be6ed5a6b745f14fbfba0f11470f49..d4890ebc298ed0863387f9f26b812b12c4be09ad 100644 (file)
--- a/arch/arm/dts/r8a774b1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -27,7 +27,6 @@
 /delete-node/ &hdmi0;
 /delete-node/ &lvds0;
 /delete-node/ &rcar_sound;
-/delete-node/ &sdhi2;
 /delete-node/ &sound_card;
 /delete-node/ &vin0;
 /delete-node/ &vin1;

diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi
index d541b48c7e384dab41ec065af054ddda5021bba3..75776decd2186f7dd586328dbba4cf44a5f538a7 100644 (file)
--- a/arch/arm/dts/r8a774b1.dtsi
+++ b/arch/arm/dts/r8a774b1.dtsi
@@ -1562,7 +1562,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2238,8 +2238,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2250,6 +2250,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 
@@ -2265,8 +2267,8 @@
                                 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
                                 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
                                 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2277,6 +2279,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 318>;
+                       iommu-map = <0 &ipmmu_hc 1 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a774c0.dtsi b/arch/arm/dts/r8a774c0.dtsi
index 151e32ac03683bf8c098f5749ff55c2c9c70e7e9..ad2e87b039acd7ac07b4c544c00f1d8b9993f677 100644 (file)
--- a/arch/arm/dts/r8a774c0.dtsi
+++ b/arch/arm/dts/r8a774c0.dtsi
@@ -49,17 +49,14 @@
                opp-shared;
                opp-800000000 {
                        opp-hz = /bits/ 64 <800000000>;
-                       opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                };
                opp-1000000000 {
                        opp-hz = /bits/ 64 <1000000000>;
-                       opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                };
                opp-1200000000 {
                        opp-hz = /bits/ 64 <1200000000>;
-                       opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                        opp-suspend;
                };
@@ -1317,7 +1314,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1707,8 +1704,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1719,6 +1716,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
index 3e9ced3b2d3349990bcad9219cd0d930f8b89576..146f78cb6f19284ca75a106cb4ed6dbc70ffb523 100644 (file)
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
@@ -14,6 +14,14 @@
        compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
 
        aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+               i2c7 = &iic_pmic;
                serial0 = &scif2;
                serial1 = &hscif0;
                serial2 = &hscif1;
@@ -51,24 +59,3 @@
        clock-names = "du.0", "du.1", "du.3",
                "dclkin.0", "dclkin.1", "dclkin.3";
 };
-
-/* Reference versaclock instead of audio_clk_a */
-&rcar_sound {
-       clocks = <&cpg CPG_MOD 1005>,
-                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                <&versaclock6_bb 4>, <&audio_clk_b>,
-                <&audio_clk_c>,
-                <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
-};

diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi
index e86287098ba778a389e92a5c7ee9415f0b747bc2..45ef5b7824094887b9c1d6f5a27017b801441ce3 100644 (file)
--- a/arch/arm/dts/r8a774e1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -30,7 +30,6 @@
 /delete-node/ &hdmi0;
 /delete-node/ &lvds0;
 /delete-node/ &rcar_sound;
-/delete-node/ &sdhi2;
 /delete-node/ &sound_card;
 /delete-node/ &vin0;
 /delete-node/ &vin1;

diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi
index c5a0e7866b2ffc7667111bb0f194efb2c6d9d458..2acf4067ab2f23e2b6624d7d39742ee92cecb1be 100644 (file)
--- a/arch/arm/dts/r8a774e1.dtsi
+++ b/arch/arm/dts/r8a774e1.dtsi
@@ -1774,7 +1774,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2471,8 +2471,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2483,6 +2483,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 
@@ -2498,8 +2500,8 @@
                                 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
                                 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
                                 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2510,6 +2512,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
                        resets = <&cpg 318>;
+                       iommu-map = <0 &ipmmu_hc 1 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
index db171e3c62f25eb879ab7f2755832bd455e16547..46fb81f5062ff6bc6a939ccde667bccdc101e59d 100644 (file)
--- a/arch/arm/dts/r8a7790.dtsi
+++ b/arch/arm/dts/r8a7790.dtsi
@@ -376,6 +376,17 @@
                        reg = <0 0xe6060000 0 0x250>;
                };
 
+               tpu: pwm@e60f0000 {
+                       compatible = "renesas,tpu-r8a7790", "renesas,tpu";
+                       reg = <0 0xe60f0000 0 0x148>;
+                       interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 304>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 304>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
+               };
+
                cpg: clock-controller@e6150000 {
                        compatible = "renesas,r8a7790-cpg-mssr";
                        reg = <0 0xe6150000 0 0x1000>;
@@ -1037,6 +1048,76 @@
                        status = "disabled";
                };
 
+               pwm0: pwm@e6e30000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e30000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm1: pwm@e6e31000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e31000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm2: pwm@e6e32000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e32000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm3: pwm@e6e33000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e33000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm4: pwm@e6e34000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e34000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm5: pwm@e6e35000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e35000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm6: pwm@e6e36000 {
+                       compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+                       reg = <0 0xe6e36000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
                can0: can@e6e80000 {
                        compatible = "renesas,can-r8a7790",
                                     "renesas,rcar-gen2-can";
@@ -1109,7 +1190,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
@@ -1252,7 +1333,7 @@
                                        dma-names = "rx", "tx", "rxu", "txu";
                                };
                                ssi1: ssi-1 {
-                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                       interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&audma0 0x03>, <&audma1 0x04>,
                                               <&audma0 0x49>, <&audma1 0x4a>;
                                        dma-names = "rx", "tx", "rxu", "txu";

diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi
index d8f91d9f42aeed8a024bf5b6b4f7bf6db01fd176..b9d34147628e120125fe85f451c666cc55442bf1 100644 (file)
--- a/arch/arm/dts/r8a7791.dtsi
+++ b/arch/arm/dts/r8a7791.dtsi
@@ -1223,7 +1223,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
@@ -1365,7 +1365,7 @@
                                        dma-names = "rx", "tx", "rxu", "txu";
                                };
                                ssi1: ssi-1 {
-                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                       interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&audma0 0x03>, <&audma1 0x04>,
                                               <&audma0 0x49>, <&audma1 0x4a>;
                                        dma-names = "rx", "tx", "rxu", "txu";

diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi
index 9ebe7bfaf0ed0a3a0474fd908d19269b5e43cc4f..f51bf687f4bd55d3e40bbc70fa3601dad9ca45a3 100644 (file)
--- a/arch/arm/dts/r8a7793.dtsi
+++ b/arch/arm/dts/r8a7793.dtsi
@@ -988,7 +988,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
@@ -1111,7 +1111,7 @@
                                        dma-names = "rx", "tx", "rxu", "txu";
                                };
                                ssi1: ssi-1 {
-                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                       interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&audma0 0x03>, <&audma1 0x04>,
                                               <&audma0 0x49>, <&audma1 0x4a>;
                                        dma-names = "rx", "tx", "rxu", "txu";

diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi
index 7aa781ff3bff695234c0c0d072e5d52bd6398c5a..371dd4715ddef83d9486564a87830e4684a752ea 100644 (file)
--- a/arch/arm/dts/r8a7794.dtsi
+++ b/arch/arm/dts/r8a7794.dtsi
@@ -955,7 +955,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;

diff --git a/arch/arm/dts/r8a77951.dtsi b/arch/arm/dts/r8a77951.dtsi
index 07c8763c1e77fc8a73ef081c90cc564ebe045b66..6d15229d25ab101d32436950ecda3f589d7f953b 100644 (file)
--- a/arch/arm/dts/r8a77951.dtsi
+++ b/arch/arm/dts/r8a77951.dtsi
@@ -75,7 +75,6 @@
                        opp-hz = /bits/ 64 <1600000000>;
                        opp-microvolt = <900000>;
                        clock-latency-ns = <300000>;
-                       turbo-mode;
                };
                opp-1700000000 {
                        opp-hz = /bits/ 64 <1700000000>;
@@ -1998,7 +1997,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2779,8 +2778,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2791,6 +2790,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 
@@ -2806,8 +2807,8 @@
                                 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
                                 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
                                 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2818,6 +2819,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                        resets = <&cpg 318>;
+                       iommu-map = <0 &ipmmu_hc 1 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a77960.dtsi b/arch/arm/dts/r8a77960.dtsi
index 1424d4ad941f44b4011311fe12a9dde3715d0c93..17062ec506beabd5a27a51b3958eda28577b09bf 100644 (file)
--- a/arch/arm/dts/r8a77960.dtsi
+++ b/arch/arm/dts/r8a77960.dtsi
@@ -70,13 +70,11 @@
                        opp-hz = /bits/ 64 <1600000000>;
                        opp-microvolt = <900000>;
                        clock-latency-ns = <300000>;
-                       turbo-mode;
                };
                opp-1700000000 {
                        opp-hz = /bits/ 64 <1700000000>;
                        opp-microvolt = <900000>;
                        clock-latency-ns = <300000>;
-                       turbo-mode;
                };
                opp-1800000000 {
                        opp-hz = /bits/ 64 <1800000000>;
@@ -1870,7 +1868,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2567,8 +2565,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2579,6 +2577,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 
@@ -2594,8 +2594,8 @@
                                 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
                                 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
                                 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2606,6 +2606,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                        resets = <&cpg 318>;
+                       iommu-map = <0 &ipmmu_hc 1 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi
index 997f29521f66c35433fcf28de56046bbf2097586..c7582003849135cd0b981a150301e488ead6e864 100644 (file)
--- a/arch/arm/dts/r8a77965.dtsi
+++ b/arch/arm/dts/r8a77965.dtsi
@@ -75,13 +75,11 @@
                        opp-hz = /bits/ 64 <1600000000>;
                        opp-microvolt = <900000>;
                        clock-latency-ns = <300000>;
-                       turbo-mode;
                };
                opp-1700000000 {
                        opp-hz = /bits/ 64 <1700000000>;
                        opp-microvolt = <900000>;
                        clock-latency-ns = <300000>;
-                       turbo-mode;
                };
                opp-1800000000 {
                        opp-hz = /bits/ 64 <1800000000>;
@@ -1733,7 +1731,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2425,8 +2423,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2437,6 +2435,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 
@@ -2452,8 +2452,8 @@
                                 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
                                 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
                                 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2464,6 +2464,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
                        resets = <&cpg 318>;
+                       iommu-map = <0 &ipmmu_hc 1 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts
index 004a5eacd460da9517be440663cf7fd080fd2b1b..405404c0843d9747aeffc014d52a07db5144415e 100644 (file)
--- a/arch/arm/dts/r8a77970-eagle.dts
+++ b/arch/arm/dts/r8a77970-eagle.dts
@@ -287,6 +287,9 @@
 };
 
 &pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
        avb_pins: avb0 {
                groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
                function = "avb0";
@@ -316,6 +319,11 @@
                groups = "scif0_data";
                function = "scif0";
        };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk_b";
+               function = "scif_clk";
+       };
 };
 
 &rpc {
@@ -391,3 +399,7 @@
 
        status = "okay";
 };
+
+&scif_clk {
+       clock-frequency = <14745600>;
+};

diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
index 1d326552e2facd06b93fe0e0cd21d48c8c7f60c9..68d1f1d53b3a38b41d69609dbdf9e15072323b13 100644 (file)
--- a/arch/arm/dts/r8a77980-condor.dts
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -14,3 +14,11 @@
        model = "Renesas Condor board based on r8a77980";
        compatible = "renesas,condor", "renesas,r8a77980";
 };
+
+&i2c0 {
+       eeprom@50 {
+               compatible = "rohm,br24t01", "atmel,24c01";
+               reg = <0x50>;
+               pagesize = <8>;
+       };
+};

diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts
index d168b0e7747d349428956cc267491f398768c2ee..77d22df25fffac6d41e9ca64c7f2fb39ee91580b 100644 (file)
--- a/arch/arm/dts/r8a77980-v3hsk.dts
+++ b/arch/arm/dts/r8a77980-v3hsk.dts
@@ -122,6 +122,7 @@
        phy0: ethernet-phy@0 {
                compatible = "ethernet-phy-id0022.1622",
                             "ethernet-phy-ieee802.3-c22";
+               rxc-skew-ps = <1500>;
                reg = <0>;
                interrupt-parent = <&gpio4>;
                interrupts = <23 IRQ_TYPE_LEVEL_LOW>;

diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
index c4ac28a0f7161d000714571af0cb6b44fa01ec21..5ed2daaca1f006493f037e7e84a782161d904219 100644 (file)
--- a/arch/arm/dts/r8a77980.dtsi
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -1386,7 +1386,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -1399,6 +1400,8 @@
                        resets = <&cpg 319>;
                        phys = <&pcie_phy>;
                        phy-names = "pcie";
+                       iommu-map = <0 &ipmmu_vi0 5 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 3053b4b2149788c6ace5958bb7fd2616a18f4546..1be0b99c15ed6680a7a3de0aa2c0e37c332894a3 100644 (file)
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -49,17 +49,14 @@
                opp-shared;
                opp-800000000 {
                        opp-hz = /bits/ 64 <800000000>;
-                       opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                };
                opp-1000000000 {
                        opp-hz = /bits/ 64 <1000000000>;
-                       opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                };
                opp-1200000000 {
                        opp-hz = /bits/ 64 <1200000000>;
-                       opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                        opp-suspend;
                };
@@ -1469,7 +1466,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1873,8 +1870,8 @@
                                 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
                                 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
                                 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                       /* Map all possible DDR as inbound ranges */
-                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+                       /* Map all possible DDR/IOMMU as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1885,6 +1882,8 @@
                        clock-names = "pcie", "pcie_bus";
                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                        resets = <&cpg 319>;
+                       iommu-map = <0 &ipmmu_hc 0 1>;
+                       iommu-map-mask = <0>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi
index f040d03e0a87ad7717e35493f636900abef883ff..e25024a7b66ccbe3ec136c68032a6a1bdf01f45c 100644 (file)
--- a/arch/arm/dts/r8a77995.dtsi
+++ b/arch/arm/dts/r8a77995.dtsi
@@ -1037,7 +1037,7 @@
 
                rcar_sound: sound@ec500000 {
                        /*
-                        * #sound-dai-cells is required
+                        * #sound-dai-cells is required if simple-card
                         *
                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;

diff --git a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
index e06b8eda85e18155ebcaccc314dad1dab59e56b1..dbc8dcab109d15db556bd079b66642b3af6dfa18 100644 (file)
--- a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
@@ -5,6 +5,8 @@
  * Copyright (C) 2021 Glider bv
  */
 
+#include <dt-bindings/media/video-interfaces.h>
+
 &csi40 {
        status = "okay";
 
@@ -105,6 +107,7 @@
                        port@4 {
                                reg = <4>;
                                max96712_out0: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                                        clock-lanes = <0>;
                                        data-lanes = <1 2 3 4>;
                                        remote-endpoint = <&csi40_in>;
@@ -125,6 +128,7 @@
                        port@4 {
                                reg = <4>;
                                max96712_out1: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                                        clock-lanes = <0>;
                                        data-lanes = <1 2 3 4>;
                                        lane-polarities = <0 0 0 0 1>;
@@ -146,6 +150,7 @@
                        port@4 {
                                reg = <4>;
                                max96712_out2: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                                        clock-lanes = <0>;
                                        data-lanes = <1 2 3 4>;
                                        lane-polarities = <0 0 0 0 1>;

diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts
index b2e67b82caf6ec3402071c1e3ce849c57d813533..63db822e5f4662b659786568cd2288c1c331e18f 100644 (file)
--- a/arch/arm/dts/r8a779a0-falcon.dts
+++ b/arch/arm/dts/r8a779a0-falcon.dts
@@ -37,8 +37,12 @@
        };
 };
 
+&can_clk {
+       clock-frequency = <40000000>;
+};
+
 &canfd {
-       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
+       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
        pinctrl-names = "default";
        status = "okay";
 
@@ -80,6 +84,11 @@
 
        };
 
+       can_clk_pins: can-clk {
+               groups = "can_clk";
+               function = "can_clk";
+       };
+
        canfd0_pins: canfd0 {
                groups = "canfd0_data";
                function = "canfd0";

diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi
index ed9400f903c9ecefde6a268fcb0b4d739b87303b..4e67a03564971b89a5b2fb7564b2eb93aa549819 100644 (file)
--- a/arch/arm/dts/r8a779a0.dtsi
+++ b/arch/arm/dts/r8a779a0.dtsi
@@ -606,7 +606,8 @@
                };
 
                canfd: can@e6660000 {
-                       compatible = "renesas,r8a779a0-canfd";
+                       compatible = "renesas,r8a779a0-canfd",
+                                    "renesas,rcar-gen4-canfd";
                        reg = <0 0xe6660000 0 0x8000>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -656,7 +657,7 @@
 
                avb0: ethernet@e6800000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6800000 0 0x800>;
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
@@ -704,7 +705,7 @@
 
                avb1: ethernet@e6810000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6810000 0 0x800>;
                        interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
@@ -752,7 +753,7 @@
 
                avb2: ethernet@e6820000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6820000 0 0x1000>;
                        interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@@ -800,7 +801,7 @@
 
                avb3: ethernet@e6830000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6830000 0 0x1000>;
                        interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,7 +849,7 @@
 
                avb4: ethernet@e6840000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6840000 0 0x1000>;
                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
@@ -896,7 +897,7 @@
 
                avb5: ethernet@e6850000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6850000 0 0x1000>;
                        interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
@@ -942,6 +943,56 @@
                        status = "disabled";
                };
 
+               pwm0: pwm@e6e30000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e30000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm1: pwm@e6e31000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e31000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm2: pwm@e6e32000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e32000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm3: pwm@e6e33000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e33000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm4: pwm@e6e34000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e34000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
                scif0: serial@e6e60000 {
                        compatible = "renesas,scif-r8a779a0",
                                     "renesas,rcar-gen4-scif", "renesas,scif";
@@ -1019,7 +1070,7 @@
 
                msiof0: spi@e6e90000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6e90000 0 0x0064>;
                        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 618>;
@@ -1034,7 +1085,7 @@
 
                msiof1: spi@e6ea0000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6ea0000 0 0x0064>;
                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 619>;
@@ -1049,7 +1100,7 @@
 
                msiof2: spi@e6c00000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c00000 0 0x0064>;
                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 620>;
@@ -1064,7 +1115,7 @@
 
                msiof3: spi@e6c10000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c10000 0 0x0064>;
                        interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 621>;
@@ -1079,7 +1130,7 @@
 
                msiof4: spi@e6c20000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c20000 0 0x0064>;
                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 622>;
@@ -1094,7 +1145,7 @@
 
                msiof5: spi@e6c28000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c28000 0 0x0064>;
                        interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 623>;
@@ -2097,7 +2148,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xee480000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 10>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2106,7 +2157,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xee4c0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 19>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2115,7 +2166,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 0>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2124,7 +2175,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed40000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 1>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2133,7 +2184,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed80000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 3>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_A3IR>;
                        #iommu-cells = <1>;
                };
@@ -2142,7 +2193,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeedc0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 12>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2151,7 +2202,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeee80000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 14>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2160,7 +2211,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeeec0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 15>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2169,7 +2220,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeee00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 6>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2178,7 +2229,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeef00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 5>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2187,7 +2238,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeef40000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 11>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2209,8 +2260,7 @@
                        interrupt-controller;
                        reg = <0x0 0xf1000000 0 0x20000>,
                              <0x0 0xf1060000 0 0x110000>;
-                       interrupts = <GIC_PPI 9
-                                     (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                fcpvd0: fcp@fea10000 {
@@ -2857,9 +2907,9 @@
 
        timer {
                compatible = "arm,armv8-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
        };
 };

diff --git a/arch/arm/dts/r8a779f0.dtsi b/arch/arm/dts/r8a779f0.dtsi
index f20b612b2b9a93a501e5b2db68dddb1aec69a3f9..1d5426e6293c561698f1a6cf3519c65b44d570bc 100644 (file)
--- a/arch/arm/dts/r8a779f0.dtsi
+++ b/arch/arm/dts/r8a779f0.dtsi
@@ -1059,7 +1059,7 @@
                        compatible = "renesas,ipmmu-r8a779f0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xee480000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 10>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -1068,7 +1068,7 @@
                        compatible = "renesas,ipmmu-r8a779f0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xee4c0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 19>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -1077,7 +1077,7 @@
                        compatible = "renesas,ipmmu-r8a779f0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 0>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -1086,7 +1086,7 @@
                        compatible = "renesas,ipmmu-r8a779f0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed40000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 2>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -1108,8 +1108,7 @@
                        interrupt-controller;
                        reg = <0x0 0xf1000000 0 0x20000>,
                              <0x0 0xf1060000 0 0x110000>;
-                       interrupts = <GIC_PPI 9
-                                     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                prr: chipid@fff00044 {
@@ -1119,7 +1118,7 @@
        };
 
        thermal-zones {
-               sensor_thermal1: sensor1-thermal {
+               sensor_thermal_rtcore: sensor1-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
                        thermal-sensors = <&tsc 0>;
@@ -1133,7 +1132,7 @@
                        };
                };
 
-               sensor_thermal2: sensor2-thermal {
+               sensor_thermal_apcore0: sensor2-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
                        thermal-sensors = <&tsc 1>;
@@ -1147,7 +1146,7 @@
                        };
                };
 
-               sensor_thermal3: sensor3-thermal {
+               sensor_thermal_apcore4: sensor3-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
                        thermal-sensors = <&tsc 2>;
@@ -1164,10 +1163,10 @@
 
        timer {
                compatible = "arm,armv8-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
        };
 
        ufs30_clk: ufs30-clk {

diff --git a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
index ae7522b60e5dbad16c0a61767117ee9841f267a7..f8537f7ea4defabad1c5327948a6749a694d427b 100644 (file)
--- a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
@@ -5,7 +5,63 @@
  * Copyright (C) 2022 Glider bv
  */
 
+#include <dt-bindings/media/video-interfaces.h>
+
+&csi40 {
+       status = "okay";
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+
+                       csi40_in: endpoint {
+                               bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+                               clock-lanes = <0>;
+                               data-lanes = <1 2 3>;
+                               remote-endpoint = <&max96712_out0>;
+                       };
+               };
+       };
+};
+
+&csi41 {
+       status = "okay";
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+
+                       csi41_in: endpoint {
+                               bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+                               clock-lanes = <0>;
+                               data-lanes = <1 2 3>;
+                               remote-endpoint = <&max96712_out1>;
+                       };
+               };
+       };
+};
+
 &i2c0 {
+       pca9654_a: gpio@21 {
+               compatible = "onnn,pca9654";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9654_b: gpio@22 {
+               compatible = "onnn,pca9654";
+               reg = <0x22>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
        eeprom@52 {
                compatible = "rohm,br24g01", "atmel,24c01";
                label = "csi-dsi-sub-board-id";
@@ -13,3 +69,119 @@
                pagesize = <8>;
        };
 };
+
+&i2c1 {
+       gmsl0: gmsl-deserializer@49 {
+               compatible = "maxim,max96712";
+               reg = <0x49>;
+               enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@4 {
+                               reg = <4>;
+                               max96712_out0: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+                                       clock-lanes = <0>;
+                                       data-lanes = <1 2 3>;
+                                       remote-endpoint = <&csi40_in>;
+                               };
+                       };
+               };
+       };
+
+       gmsl1: gmsl-deserializer@4b {
+               compatible = "maxim,max96712";
+               reg = <0x4b>;
+               enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@4 {
+                               reg = <4>;
+                               max96712_out1: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+                                       clock-lanes = <0>;
+                                       data-lanes = <1 2 3>;
+                                       remote-endpoint = <&csi41_in>;
+                               };
+                       };
+               };
+       };
+};
+
+&isp0 {
+       status = "okay";
+};
+
+&isp1 {
+       status = "okay";
+};
+
+&vin00 {
+       status = "okay";
+};
+
+&vin01 {
+       status = "okay";
+};
+
+&vin02 {
+       status = "okay";
+};
+
+&vin03 {
+       status = "okay";
+};
+
+&vin04 {
+       status = "okay";
+};
+
+&vin05 {
+       status = "okay";
+};
+
+&vin06 {
+       status = "okay";
+};
+
+&vin07 {
+       status = "okay";
+};
+
+&vin08 {
+       status = "okay";
+};
+
+&vin09 {
+       status = "okay";
+};
+
+&vin10 {
+       status = "okay";
+};
+
+&vin11 {
+       status = "okay";
+};
+
+&vin12 {
+       status = "okay";
+};
+
+&vin13 {
+       status = "okay";
+};
+
+&vin14 {
+       status = "okay";
+};
+
+&vin15 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/r8a779g0-white-hawk.dts b/arch/arm/dts/r8a779g0-white-hawk.dts
index 04a2b6b83e743f326c9b88d8c98c915175512254..eff1ef6e2cc83aba94d041996682b3616002c1be 100644 (file)
--- a/arch/arm/dts/r8a779g0-white-hawk.dts
+++ b/arch/arm/dts/r8a779g0-white-hawk.dts
@@ -13,6 +13,33 @@
 / {
        model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
        compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+       can_transceiver0: can-phy0 {
+               compatible = "nxp,tjr1443";
+               #phy-cells = <0>;
+               enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+               max-bitrate = <5000000>;
+       };
+};
+
+&can_clk {
+       clock-frequency = <40000000>;
+};
+
+&canfd {
+       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       channel0 {
+               status = "okay";
+               phys = <&can_transceiver0>;
+       };
+
+       channel1 {
+               status = "okay";
+       };
 };
 
 &i2c0 {
@@ -23,3 +50,20 @@
                pagesize = <8>;
        };
 };
+
+&pfc {
+       can_clk_pins: can-clk {
+               groups = "can_clk";
+               function = "can_clk";
+       };
+
+       canfd0_pins: canfd0 {
+               groups = "canfd0_data";
+               function = "canfd0";
+       };
+
+       canfd1_pins: canfd1 {
+               groups = "canfd1_data";
+               function = "canfd1";
+       };
+};

diff --git a/arch/arm/dts/r8a779g0.dtsi b/arch/arm/dts/r8a779g0.dtsi
index 7a87a5dc1b6ad21907c2c658dec28ba55fcf745f..d3d25e077c5d50531baf7d0dc2925f35f2dbc4c1 100644 (file)
--- a/arch/arm/dts/r8a779g0.dtsi
+++ b/arch/arm/dts/r8a779g0.dtsi
@@ -14,6 +14,20 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       /* External Audio clock - to be overridden by boards that provide it */
+       audio_clkin: audio_clkin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       /* External CAN clock - to be overridden by boards that provide it */
+       can_clk: can {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
        cluster0_opp: opp-table-0 {
                compatible = "operating-points-v2";
                opp-shared;
@@ -431,6 +445,18 @@
                        #power-domain-cells = <1>;
                };
 
+               tsc: thermal@e6198000 {
+                       compatible = "renesas,r8a779g0-thermal";
+                       reg = <0 0xe6198000 0 0x200>,
+                             <0 0xe61a0000 0 0x200>,
+                             <0 0xe61a8000 0 0x200>,
+                             <0 0xe61b0000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 919>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 919>;
+                       #thermal-sensor-cells = <1>;
+               };
+
                intc_ex: interrupt-controller@e61c0000 {
                        compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
                        #interrupt-cells = <2>;
@@ -682,6 +708,56 @@
                        status = "disabled";
                };
 
+               canfd: can@e6660000 {
+                       compatible = "renesas,r8a779g0-canfd",
+                                    "renesas,rcar-gen4-canfd";
+                       reg = <0 0xe6660000 0 0x8500>;
+                       interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "ch_int", "g_int";
+                       clocks = <&cpg CPG_MOD 328>,
+                                <&cpg CPG_CORE R8A779G0_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "fck", "canfd", "can_clk";
+                       assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>;
+                       assigned-clock-rates = <80000000>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 328>;
+                       status = "disabled";
+
+                       channel0 {
+                               status = "disabled";
+                       };
+
+                       channel1 {
+                               status = "disabled";
+                       };
+
+                       channel2 {
+                               status = "disabled";
+                       };
+
+                       channel3 {
+                               status = "disabled";
+                       };
+
+                       channel4 {
+                               status = "disabled";
+                       };
+
+                       channel5 {
+                               status = "disabled";
+                       };
+
+                       channel6 {
+                               status = "disabled";
+                       };
+
+                       channel7 {
+                               status = "disabled";
+                       };
+               };
+
                avb0: ethernet@e6800000 {
                        compatible = "renesas,etheravb-r8a779g0",
                                     "renesas,etheravb-rcar-gen4";
@@ -1098,6 +1174,454 @@
                        status = "disabled";
                };
 
+               vin00: video@e6ef0000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef0000 0 0x1000>;
+                       interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 730>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 730>;
+                       renesas,id = <0>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin00isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin00>;
+                                       };
+                               };
+                       };
+               };
+
+               vin01: video@e6ef1000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef1000 0 0x1000>;
+                       interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 731>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 731>;
+                       renesas,id = <1>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin01isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin01>;
+                                       };
+                               };
+                       };
+               };
+
+               vin02: video@e6ef2000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef2000 0 0x1000>;
+                       interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 800>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 800>;
+                       renesas,id = <2>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin02isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin02>;
+                                       };
+                               };
+                       };
+               };
+
+               vin03: video@e6ef3000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef3000 0 0x1000>;
+                       interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 801>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 801>;
+                       renesas,id = <3>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin03isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin03>;
+                                       };
+                               };
+                       };
+               };
+
+               vin04: video@e6ef4000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef4000 0 0x1000>;
+                       interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 802>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 802>;
+                       renesas,id = <4>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin04isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin04>;
+                                       };
+                               };
+                       };
+               };
+
+               vin05: video@e6ef5000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef5000 0 0x1000>;
+                       interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 803>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 803>;
+                       renesas,id = <5>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin05isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin05>;
+                                       };
+                               };
+                       };
+               };
+
+               vin06: video@e6ef6000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef6000 0 0x1000>;
+                       interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 804>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 804>;
+                       renesas,id = <6>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin06isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin06>;
+                                       };
+                               };
+                       };
+               };
+
+               vin07: video@e6ef7000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef7000 0 0x1000>;
+                       interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 805>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 805>;
+                       renesas,id = <7>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin07isp0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&isp0vin07>;
+                                       };
+                               };
+                       };
+               };
+
+               vin08: video@e6ef8000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef8000 0 0x1000>;
+                       interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 806>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 806>;
+                       renesas,id = <8>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin08isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin08>;
+                                       };
+                               };
+                       };
+               };
+
+               vin09: video@e6ef9000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6ef9000 0 0x1000>;
+                       interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 807>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 807>;
+                       renesas,id = <9>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin09isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin09>;
+                                       };
+                               };
+                       };
+               };
+
+               vin10: video@e6efa000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6efa000 0 0x1000>;
+                       interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 808>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 808>;
+                       renesas,id = <10>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin10isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin10>;
+                                       };
+                               };
+                       };
+               };
+
+               vin11: video@e6efb000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6efb000 0 0x1000>;
+                       interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 809>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 809>;
+                       renesas,id = <11>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin11isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin11>;
+                                       };
+                               };
+                       };
+               };
+
+               vin12: video@e6efc000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6efc000 0 0x1000>;
+                       interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 810>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 810>;
+                       renesas,id = <12>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin12isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin12>;
+                                       };
+                               };
+                       };
+               };
+
+               vin13: video@e6efd000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6efd000 0 0x1000>;
+                       interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 811>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 811>;
+                       renesas,id = <13>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin13isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin13>;
+                                       };
+                               };
+                       };
+               };
+
+               vin14: video@e6efe000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6efe000 0 0x1000>;
+                       interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 812>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 812>;
+                       renesas,id = <14>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin14isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin14>;
+                                       };
+                               };
+                       };
+               };
+
+               vin15: video@e6eff000 {
+                       compatible = "renesas,vin-r8a779g0";
+                       reg = <0 0xe6eff000 0 0x1000>;
+                       interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 813>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 813>;
+                       renesas,id = <15>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <2>;
+
+                                       vin15isp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&isp1vin15>;
+                                       };
+                               };
+                       };
+               };
+
                dmac0: dma-controller@e7350000 {
                        compatible = "renesas,dmac-r8a779g0",
                                     "renesas,rcar-gen4-dmac";
@@ -1131,6 +1655,14 @@
                        resets = <&cpg 709>;
                        #dma-cells = <1>;
                        dma-channels = <16>;
+                       iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+                                <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+                                <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+                                <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+                                <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+                                <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+                                <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+                                <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
                };
 
                dmac1: dma-controller@e7351000 {
@@ -1166,6 +1698,192 @@
                        resets = <&cpg 710>;
                        #dma-cells = <1>;
                        dma-channels = <16>;
+                       iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
+                                <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
+                                <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
+                                <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
+                                <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
+                                <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
+                                <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
+                                <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
+               };
+
+               rcar_sound: sound@ec5a0000 {
+                       /*
+                        * #sound-dai-cells is required
+                        *
+                        * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+                        * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+                        */
+                       /*
+                        * #clock-cells is required
+                        *
+                        * clkout               : #clock-cells = <0>;   <&rcar_sound>;
+                        * audio_clkout0/1/2/3  : #clock-cells = <1>;   <&rcar_sound N>;
+                        */
+                       compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4";
+                       reg = <0 0xec5a0000 0 0x020>,
+                             <0 0xec540000 0 0x1000>,
+                             <0 0xec541000 0 0x050>,
+                             <0 0xec400000 0 0x40000>;
+                       reg-names = "adg", "ssiu", "ssi", "sdmc";
+
+                       clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>;
+                       clock-names = "ssiu.0", "ssi.0", "clkin";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 2926>, <&cpg 2927>;
+                       reset-names = "ssiu.0", "ssi.0";
+                       status = "disabled";
+
+                       rcar_sound,ssiu {
+                               ssiu00: ssiu-0 {
+                                       dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu01: ssiu-1 {
+                                       dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu02: ssiu-2 {
+                                       dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu03: ssiu-3 {
+                                       dmas = <&dmac0 0x68>, <&dmac0 0x69>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu04: ssiu-4 {
+                                       dmas = <&dmac0 0x66>, <&dmac0 0x67>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu05: ssiu-5 {
+                                       dmas = <&dmac0 0x64>, <&dmac0 0x65>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu06: ssiu-6 {
+                                       dmas = <&dmac0 0x62>, <&dmac0 0x63>;
+                                       dma-names = "tx", "rx";
+                               };
+                               ssiu07: ssiu-7 {
+                                       dmas = <&dmac0 0x60>, <&dmac0 0x61>;
+                                       dma-names = "tx", "rx";
+                               };
+                       };
+
+                       rcar_sound,ssi {
+                               ssi0: ssi-0 {
+                                       interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                       };
+               };
+
+               ipmmu_rt0: iommu@ee480000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xee480000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_rt1: iommu@ee4c0000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xee4c0000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_ds0: iommu@eed00000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeed00000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_hc: iommu@eed40000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeed40000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_ir: iommu@eed80000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeed80000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_A3IR>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_vc: iommu@eedc0000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeedc0000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_3dg: iommu@eee00000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeee00000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_vi0: iommu@eee80000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeee80000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_vi1: iommu@eeec0000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeeec0000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_vip0: iommu@eef00000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeef00000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_vip1: iommu@eef40000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeef40000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_mm: iommu@eefc0000 {
+                       compatible = "renesas,ipmmu-r8a779g0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeefc0000 0 0x20000>;
+                       interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
                };
 
                mmc0: mmc@ee140000 {
@@ -1179,6 +1897,7 @@
                        power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
                        resets = <&cpg 706>;
                        max-frequency = <200000000>;
+                       iommus = <&ipmmu_ds0 32>;
                        status = "disabled";
                };
 
@@ -1205,8 +1924,59 @@
                        interrupt-controller;
                        reg = <0x0 0xf1000000 0 0x20000>,
                              <0x0 0xf1060000 0 0x110000>;
-                       interrupts = <GIC_PPI 9
-                                     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               csi40: csi2@fe500000 {
+                       compatible = "renesas,r8a779g0-csi2";
+                       reg = <0 0xfe500000 0 0x40000>;
+                       interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 331>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 331>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       csi40isp0: endpoint {
+                                               remote-endpoint = <&isp0csi40>;
+                                       };
+                               };
+                       };
+               };
+
+               csi41: csi2@fe540000 {
+                       compatible = "renesas,r8a779g0-csi2";
+                       reg = <0 0xfe540000 0 0x40000>;
+                       interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 400>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 400>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       csi41isp1: endpoint {
+                                               remote-endpoint = <&isp1csi41>;
+                                       };
+                               };
+                       };
                };
 
                fcpvd0: fcp@fea10000 {
@@ -1281,6 +2051,172 @@
                        };
                };
 
+               isp0: isp@fed00000 {
+                       compatible = "renesas,r8a779g0-isp";
+                       reg = <0 0xfed00000 0 0x10000>;
+                       interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&cpg CPG_MOD 612>;
+                       power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+                       resets = <&cpg 612>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <0>;
+
+                                       isp0csi40: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&csi40isp0>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       isp0vin00: endpoint {
+                                               remote-endpoint = <&vin00isp0>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       isp0vin01: endpoint {
+                                               remote-endpoint = <&vin01isp0>;
+                                       };
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       isp0vin02: endpoint {
+                                               remote-endpoint = <&vin02isp0>;
+                                       };
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                                       isp0vin03: endpoint {
+                                               remote-endpoint = <&vin03isp0>;
+                                       };
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                                       isp0vin04: endpoint {
+                                               remote-endpoint = <&vin04isp0>;
+                                       };
+                               };
+
+                               port@6 {
+                                       reg = <6>;
+                                       isp0vin05: endpoint {
+                                               remote-endpoint = <&vin05isp0>;
+                                       };
+                               };
+
+                               port@7 {
+                                       reg = <7>;
+                                       isp0vin06: endpoint {
+                                               remote-endpoint = <&vin06isp0>;
+                                       };
+                               };
+
+                               port@8 {
+                                       reg = <8>;
+                                       isp0vin07: endpoint {
+                                               remote-endpoint = <&vin07isp0>;
+                                       };
+                               };
+                       };
+               };
+
+               isp1: isp@fed20000 {
+                       compatible = "renesas,r8a779g0-isp";
+                       reg = <0 0xfed20000 0 0x10000>;
+                       interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&cpg CPG_MOD 613>;
+                       power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+                       resets = <&cpg 613>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <0>;
+
+                                       isp1csi41: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&csi41isp1>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       isp1vin08: endpoint {
+                                               remote-endpoint = <&vin08isp1>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       isp1vin09: endpoint {
+                                               remote-endpoint = <&vin09isp1>;
+                                       };
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       isp1vin10: endpoint {
+                                               remote-endpoint = <&vin10isp1>;
+                                       };
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                                       isp1vin11: endpoint {
+                                               remote-endpoint = <&vin11isp1>;
+                                       };
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                                       isp1vin12: endpoint {
+                                               remote-endpoint = <&vin12isp1>;
+                                       };
+                               };
+
+                               port@6 {
+                                       reg = <6>;
+                                       isp1vin13: endpoint {
+                                               remote-endpoint = <&vin13isp1>;
+                                       };
+                               };
+
+                               port@7 {
+                                       reg = <7>;
+                                       isp1vin14: endpoint {
+                                               remote-endpoint = <&vin14isp1>;
+                                       };
+                               };
+
+                               port@8 {
+                                       reg = <8>;
+                                       isp1vin15: endpoint {
+                                               remote-endpoint = <&vin15isp1>;
+                                       };
+                               };
+                       };
+               };
+
                dsi0: dsi-encoder@fed80000 {
                        compatible = "renesas,r8a779g0-dsi-csi2-tx";
                        reg = <0 0xfed80000 0 0x10000>;
@@ -1345,11 +2281,69 @@
                };
        };
 
+       thermal-zones {
+               sensor_thermal_cr52: sensor1-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 0>;
+
+                       trips {
+                               sensor1_crit: sensor1-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               sensor_thermal_cnn: sensor2-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 1>;
+
+                       trips {
+                               sensor2_crit: sensor2-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               sensor_thermal_ca76: sensor3-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 2>;
+
+                       trips {
+                               sensor3_crit: sensor3-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               sensor_thermal_ddr1: sensor4-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 3>;
+
+                       trips {
+                               sensor4_crit: sensor4-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
        timer {
                compatible = "arm,armv8-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
        };
 };

diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi
index 23fdd1115b21fcaca032f441e4a27790800587bb..4a3d5037821f12f51664b6016969741325946ec1 100644 (file)
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@@ -33,9 +33,20 @@
 
 / {
        aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+               i2c7 = &i2c_dvfs;
                serial0 = &scif2;
                serial1 = &hscif1;
                ethernet0 = &avb;
+               mmc0 = &sdhi2;
+               mmc1 = &sdhi0;
+               mmc2 = &sdhi3;
        };
 
        chosen {
@@ -94,6 +105,7 @@
 
                port {
                        hdmi0_con: endpoint {
+                               remote-endpoint = <&rcar_dw_hdmi0_out>;
                        };
                };
        };
@@ -166,7 +178,7 @@
                };
        };
 
-       reg_1p8v: regulator0 {
+       reg_1p8v: regulator-1p8v {
                compatible = "regulator-fixed";
                regulator-name = "fixed-1.8V";
                regulator-min-microvolt = <1800000>;
@@ -175,7 +187,7 @@
                regulator-always-on;
        };
 
-       reg_3p3v: regulator1 {
+       reg_3p3v: regulator-3p3v {
                compatible = "regulator-fixed";
                regulator-name = "fixed-3.3V";
                regulator-min-microvolt = <3300000>;
@@ -184,7 +196,7 @@
                regulator-always-on;
        };
 
-       reg_12v: regulator2 {
+       reg_12v: regulator-12v {
                compatible = "regulator-fixed";
                regulator-name = "fixed-12V";
                regulator-min-microvolt = <12000000>;
@@ -198,7 +210,12 @@
 
                label = "rcar-sound";
 
-               dais = <&rsnd_port0>;
+               dais = <&rsnd_port0     /* ak4613 */
+                       &rsnd_port1     /* HDMI0  */
+#ifdef SOC_HAS_HDMI1
+                       &rsnd_port2     /* HDMI1  */
+#endif
+                       >;
        };
 
        vbus0_usb2: regulator-vbus0-usb2 {
@@ -316,6 +333,10 @@
        };
 };
 
+&a57_0 {
+       cpu-supply = <&dvfs>;
+};
+
 &audio_clk_a {
        clock-frequency = <22579200>;
 };
@@ -324,7 +345,7 @@
        pinctrl-0 = <&avb_pins>;
        pinctrl-names = "default";
        phy-handle = <&phy0>;
-       phy-mode = "rgmii-txid";
+       tx-internal-delay-ps = <2000>;
        status = "okay";
 
        phy0: ethernet-phy@0 {
@@ -343,7 +364,6 @@
 
        ports {
                port@0 {
-                       reg = <0>;
                        csi20_in: endpoint {
                                clock-lanes = <0>;
                                data-lanes = <1>;
@@ -358,8 +378,6 @@
 
        ports {
                port@0 {
-                       reg = <0>;
-
                        csi40_in: endpoint {
                                clock-lanes = <0>;
                                data-lanes = <1 2 3 4>;
@@ -376,7 +394,7 @@
 
        ports {
                port@0 {
-                       endpoint {
+                       du_out_rgb: endpoint {
                                remote-endpoint = <&adv7123_in>;
                        };
                };
@@ -396,6 +414,50 @@
        clock-frequency = <32768>;
 };
 
+&hdmi0 {
+       status = "okay";
+
+       ports {
+               port@1 {
+                       reg = <1>;
+                       rcar_dw_hdmi0_out: endpoint {
+                               remote-endpoint = <&hdmi0_con>;
+                       };
+               };
+               port@2 {
+                       reg = <2>;
+                       dw_hdmi0_snd_in: endpoint {
+                               remote-endpoint = <&rsnd_endpoint1>;
+                       };
+               };
+       };
+};
+
+#ifdef SOC_HAS_HDMI1
+&hdmi1 {
+       status = "okay";
+
+       ports {
+               port@1 {
+                       reg = <1>;
+                       rcar_dw_hdmi1_out: endpoint {
+                               remote-endpoint = <&hdmi1_con>;
+                       };
+               };
+               port@2 {
+                       reg = <2>;
+                       dw_hdmi1_snd_in: endpoint {
+                               remote-endpoint = <&rsnd_endpoint2>;
+                       };
+               };
+       };
+};
+
+&hdmi1_con {
+       remote-endpoint = <&rcar_dw_hdmi1_out>;
+};
+#endif /* SOC_HAS_HDMI1 */
+
 &hscif1 {
        pinctrl-0 = <&hscif1_pins>;
        pinctrl-names = "default";
@@ -469,47 +531,49 @@
                reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
                            "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                interrupt-parent = <&gpio6>;
                interrupt-names = "intrq1", "intrq2";
                interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
                             <31 IRQ_TYPE_LEVEL_LOW>;
 
-               port@7 {
-                       reg = <7>;
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@7 {
+                               reg = <7>;
 
-                       adv7482_ain7: endpoint {
-                               remote-endpoint = <&cvbs_con>;
+                               adv7482_ain7: endpoint {
+                                       remote-endpoint = <&cvbs_con>;
+                               };
                        };
-               };
 
-               port@8 {
-                       reg = <8>;
+                       port@8 {
+                               reg = <8>;
 
-                       adv7482_hdmi: endpoint {
-                               remote-endpoint = <&hdmi_in_con>;
+                               adv7482_hdmi: endpoint {
+                                       remote-endpoint = <&hdmi_in_con>;
+                               };
                        };
-               };
 
-               port@a {
-                       reg = <10>;
+                       port@a {
+                               reg = <10>;
 
-                       adv7482_txa: endpoint {
-                               clock-lanes = <0>;
-                               data-lanes = <1 2 3 4>;
-                               remote-endpoint = <&csi40_in>;
+                               adv7482_txa: endpoint {
+                                       clock-lanes = <0>;
+                                       data-lanes = <1 2 3 4>;
+                                       remote-endpoint = <&csi40_in>;
+                               };
                        };
-               };
 
-               port@b {
-                       reg = <11>;
+                       port@b {
+                               reg = <11>;
 
-                       adv7482_txb: endpoint {
-                               clock-lanes = <0>;
-                               data-lanes = <1>;
-                               remote-endpoint = <&csi20_in>;
+                               adv7482_txb: endpoint {
+                                       clock-lanes = <0>;
+                                       data-lanes = <1>;
+                                       remote-endpoint = <&csi20_in>;
+                               };
                        };
                };
        };
@@ -732,12 +796,9 @@
 };
 
 &rcar_sound {
-       pinctrl-0 = <&sound_pins &sound_clk_pins>;
+       pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
        pinctrl-names = "default";
 
-       /* Single DAI */
-       #sound-dai-cells = <0>;
-
        /* audio_clkout0/1/2/3 */
        #clock-cells = <1>;
        clock-frequency = <12288000 11289600>;
@@ -775,8 +836,85 @@
                                bitclock-master = <&rsnd_endpoint0>;
                                frame-master = <&rsnd_endpoint0>;
 
-                               playback = <&ssi0 &src0 &dvc0>;
-                               capture  = <&ssi1 &src1 &dvc1>;
+                               playback = <&ssi0>, <&src0>, <&dvc0>;
+                               capture = <&ssi1>, <&src1>, <&dvc1>;
+                       };
+               };
+
+               rsnd_port1: port@1 {
+                       reg = <1>;
+                       rsnd_endpoint1: endpoint {
+                               remote-endpoint = <&dw_hdmi0_snd_in>;
+
+                               dai-format = "i2s";
+                               bitclock-master = <&rsnd_endpoint1>;
+                               frame-master = <&rsnd_endpoint1>;
+
+                               playback = <&ssi2>;
+                       };
+               };
+
+#ifdef SOC_HAS_HDMI1
+               rsnd_port2: port@2 {
+                       reg = <2>;
+                       rsnd_endpoint2: endpoint {
+                               remote-endpoint = <&dw_hdmi1_snd_in>;
+
+                               dai-format = "i2s";
+                               bitclock-master = <&rsnd_endpoint2>;
+                               frame-master = <&rsnd_endpoint2>;
+
+                               playback = <&ssi3>;
+                       };
+               };
+#endif /* SOC_HAS_HDMI1 */
+       };
+};
+
+&rpc {
+       /* Left disabled.  To be enabled by firmware when unlocked. */
+
+       flash@0 {
+               compatible = "cypress,hyperflash", "cfi-flash";
+               reg = <0>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       bootparam@0 {
+                               reg = <0x00000000 0x040000>;
+                               read-only;
+                       };
+                       bl2@40000 {
+                               reg = <0x00040000 0x140000>;
+                               read-only;
+                       };
+                       cert_header_sa6@180000 {
+                               reg = <0x00180000 0x040000>;
+                               read-only;
+                       };
+                       bl31@1c0000 {
+                               reg = <0x001c0000 0x040000>;
+                               read-only;
+                       };
+                       tee@200000 {
+                               reg = <0x00200000 0x440000>;
+                               read-only;
+                       };
+                       uboot@640000 {
+                               reg = <0x00640000 0x100000>;
+                               read-only;
+                       };
+                       dtb@740000 {
+                               reg = <0x00740000 0x080000>;
+                       };
+                       kernel@7c0000 {
+                               reg = <0x007c0000 0x1400000>;
+                       };
+                       user@1bc0000 {
+                               reg = <0x01bc0000 0x2440000>;
                        };
                };
        };
@@ -787,6 +925,12 @@
        status = "okay";
 };
 
+#ifdef SOC_HAS_SATA
+&sata {
+       status = "okay";
+};
+#endif /* SOC_HAS_SATA */
+
 &scif1 {
        pinctrl-0 = <&scif1_pins>;
        pinctrl-names = "default";
@@ -833,8 +977,11 @@
        bus-width = <8>;
        mmc-hs200-1_8v;
        mmc-hs400-1_8v;
+       no-sd;
+       no-sdio;
        non-removable;
        fixed-emmc-driver-type = <1>;
+       full-pwr-cycle-in-suspend;
        status = "okay";
 };
 
@@ -931,3 +1078,27 @@
 
        status = "okay";
 };
+
+#ifdef SOC_HAS_USB2_CH2
+&ehci2 {
+       status = "okay";
+};
+
+&ohci2 {
+       status = "okay";
+};
+
+&pfc {
+       usb2_pins: usb2 {
+               groups = "usb2";
+               function = "usb2";
+       };
+};
+
+&usb2_phy2 {
+       pinctrl-0 = <&usb2_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+#endif /* SOC_HAS_USB2_CH2 */

diff --git a/arch/arm/dts/salvator-xs.dtsi b/arch/arm/dts/salvator-xs.dtsi
index 717d42758cbc4b399e6dc9b4af0333a62fdda5ca..08b925624e129205681d4e5feefee8596ddec2e1 100644 (file)
--- a/arch/arm/dts/salvator-xs.dtsi
+++ b/arch/arm/dts/salvator-xs.dtsi
@@ -27,3 +27,59 @@
                clock-names = "xin";
        };
 };
+
+#ifdef SOC_HAS_SATA
+&pca9654 {
+       pcie-sata-switch-hog {
+               gpio-hog;
+               gpios = <7 GPIO_ACTIVE_HIGH>;
+               output-low; /* enable SATA by default */
+               line-name = "PCIE/SATA switch";
+       };
+};
+
+/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
+#endif /* SOC_HAS_SATA */
+
+#ifdef SOC_HAS_USB2_CH3
+&ehci3 {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&hsusb3 {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&ohci3 {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&pfc {
+       /*
+        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
+        *   (when SW31 is the default setting on Salvator-XS).
+        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
+        *   r8a77951 with Salvator-XS.
+        *   Hence the SW31 setting must be changed like 2) below.
+        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
+        *      - Connect GP6_3[01] to ADV7842.
+        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
+        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
+        *      - Connect GP6_{04,21} to ADV7842.
+        */
+       usb2_ch3_pins: usb2_ch3 {
+               groups = "usb2_ch3";
+               function = "usb2_ch3";
+       };
+};
+
+&usb2_phy3 {
+       pinctrl-0 = <&usb2_ch3_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+#endif /* SOC_HAS_USB2_CH3 */

diff --git a/arch/arm/dts/ulcb-audio-graph-card.dtsi b/arch/arm/dts/ulcb-audio-graph-card.dtsi
new file mode 100644 (file)
index 0000000..3be54df
--- /dev/null
+++ b/arch/arm/dts/ulcb-audio-graph-card.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree for ULCB + Audio Graph Card
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/*
+ *     (A) CPU0 <-----> ak4613
+ *     (B) CPU1  -----> HDMI
+ *
+ *     (A) aplay   -D plughw:0,0 xxx.wav
+ *     (B) aplay   -D plughw:0,1 xxx.wav
+ *
+ *     (A) arecord -D plughw:0,0 xxx.wav
+ */
+
+/ {
+       sound_card: sound {
+               compatible = "audio-graph-card";
+               label = "rcar-sound";
+
+               dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
+                       &rsnd_port1 /* (B) CPU1  -> HDMI   */
+               >;
+       };
+};
+
+&ak4613 {
+       #sound-dai-cells = <0>;
+
+       port {
+               /*
+                * (A) CPU0 <-> ak4613
+                */
+               ak4613_endpoint: endpoint {
+                       remote-endpoint = <&rsnd_for_ak4613>;
+               };
+       };
+};
+
+&hdmi0 {
+       ports {
+               port@2 {
+                       /*
+                        * (B) CPU1 -> HDMI
+                        */
+                       dw_hdmi0_snd_in: endpoint {
+                               remote-endpoint = <&rsnd_for_hdmi>;
+                       };
+               };
+       };
+};
+
+&rcar_sound {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               rsnd_port0: port@0 {
+                       /*
+                        * (A) CPU0 <-> ak4613
+                        */
+                       reg = <0>;
+                       rsnd_for_ak4613: endpoint {
+                               remote-endpoint = <&ak4613_endpoint>;
+                               bitclock-master;
+                               frame-master;
+                               playback = <&ssi0>, <&src0>, <&dvc0>;
+                               capture  = <&ssi1>, <&src1>, <&dvc1>;
+                       };
+               };
+               rsnd_port1: port@1 {
+                       /*
+                        * (B) CPU1 -> HDMI
+                        */
+                       reg = <1>;
+                       rsnd_for_hdmi: endpoint {
+                               remote-endpoint = <&dw_hdmi0_snd_in>;
+                               bitclock-master;
+                               frame-master;
+                               playback = <&ssi2>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm/dts/ulcb-audio-graph-card2.dtsi b/arch/arm/dts/ulcb-audio-graph-card2.dtsi
new file mode 100644 (file)
index 0000000..5ebec12
--- /dev/null
+++ b/arch/arm/dts/ulcb-audio-graph-card2.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree for ULCB + Audio Graph Card2
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/*
+ *     (A) CPU0 <----> ak4613
+ *     (B) CPU1  ----> HDMI
+ *
+ *     (A) aplay   -D plughw:0,0 xxx.wav
+ *     (B) aplay   -D plughw:0,1 xxx.wav
+ *
+ *     (A) arecord -D plughw:0,0 xxx.wav
+ */
+#include "ulcb-audio-graph-card.dtsi"
+
+&sound_card {
+       compatible = "audio-graph-card2";
+
+       /delete-property/ dais;
+       links = <&rsnd_port0    /* (A) CPU0 <-> ak4613 */
+                &rsnd_port1    /* (B) CPU1  -> HDMI   */
+               >;
+};

diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
index 29cedf4dc1a9df19fa6278c3fd08d612c8fe15e2..0be2716659e96fba4a3636078ca50fcbc3e0131e 100644 (file)
--- a/arch/arm/dts/ulcb.dtsi
+++ b/arch/arm/dts/ulcb.dtsi
@@ -6,14 +6,6 @@
  * Copyright (C) 2016 Cogent Embedded, Inc.
  */
 
-/*
- * SSI-AK4613
- *     aplay   -D plughw:0,0 xxx.wav
- *     arecord -D plughw:0,0 xxx.wav
- * SSI-HDMI
- *     aplay   -D plughw:0,1 xxx.wav
- */
-
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
@@ -102,15 +94,6 @@
                regulator-always-on;
        };
 
-       sound_card: sound {
-               compatible = "audio-graph-card2";
-               label = "rcar-sound";
-
-               links = <&rsnd_port0    /* ak4613 */
-                        &rsnd_port1    /* HDMI0  */
-                       >;
-       };
-
        vcc_sdhi0: regulator-vcc-sdhi0 {
                compatible = "regulator-fixed";
 
@@ -201,9 +184,6 @@
                };
                port@2 {
                        reg = <2>;
-                       dw_hdmi0_snd_in: endpoint {
-                               remote-endpoint = <&rsnd_for_hdmi>;
-                       };
                };
        };
 };
@@ -218,7 +198,6 @@
 
        ak4613: codec@10 {
                compatible = "asahi-kasei,ak4613";
-               #sound-dai-cells = <0>;
                reg = <0x10>;
                clocks = <&rcar_sound 3>;
 
@@ -230,12 +209,6 @@
                asahi-kasei,out4-single-end;
                asahi-kasei,out5-single-end;
                asahi-kasei,out6-single-end;
-
-               port {
-                       ak4613_endpoint: endpoint {
-                               remote-endpoint = <&rsnd_for_ak4613>;
-                       };
-               };
        };
 
        cs2000: clk-multiplier@4f {
@@ -294,6 +267,12 @@
                        };
                };
        };
+
+       eeprom@50 {
+               compatible = "rohm,br24t01", "atmel,24c01";
+               reg = <0x50>;
+               pagesize = <8>;
+       };
 };
 
 &ohci1 {
@@ -381,9 +360,6 @@
        pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
        pinctrl-names = "default";
 
-       /* Single DAI */
-       #sound-dai-cells = <0>;
-
        /* audio_clkout0/1/2/3 */
        #clock-cells = <1>;
        clock-frequency = <12288000 11289600>;
@@ -408,30 +384,6 @@
                 <&audio_clk_a>, <&cs2000>,
                 <&audio_clk_c>,
                 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-
-       ports {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               rsnd_port0: port@0 {
-                       reg = <0>;
-                       rsnd_for_ak4613: endpoint {
-                               remote-endpoint = <&ak4613_endpoint>;
-                               bitclock-master;
-                               frame-master;
-                               playback = <&ssi0>, <&src0>, <&dvc0>;
-                               capture = <&ssi1>, <&src1>, <&dvc1>;
-                       };
-               };
-               rsnd_port1: port@1 {
-                       reg = <1>;
-                       rsnd_for_hdmi: endpoint {
-                               remote-endpoint = <&dw_hdmi0_snd_in>;
-                               bitclock-master;
-                               frame-master;
-                               playback = <&ssi2>;
-                       };
-               };
-       };
 };
 
 &rpc {
@@ -541,3 +493,17 @@
 
        status = "okay";
 };
+
+
+/*
+ * For sound-test.
+ *
+ * We can switch Audio Card for testing
+ *
+ * #include "ulcb-simple-audio-card.dtsi"
+ * #include "ulcb-simple-audio-card-mix+split.dtsi"
+ * #include "ulcb-audio-graph-card.dtsi"
+ * #include "ulcb-audio-graph-card-mix+split.dtsi"
+ * #include "ulcb-audio-graph-card2-mix+split.dtsi"
+ */
+#include "ulcb-audio-graph-card2.dtsi"

diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 58e92f442d5c98bfc9589ce9fbd4b1ebccaff46e..e045cf27d3c5ecac83dc8da4b4e6f1e14b0087f2 100644 (file)
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -58,7 +58,6 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_SYS_MMC_ENV_PART=2
 CONFIG_VERSION_VARIABLE=y
 CONFIG_REGMAP=y

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 1f76d6b2c2e61fa993fe19452d0dd60b72f3550f..6280061af891ee983863328eef67f83e021ec2fa 100644 (file)
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -47,7 +47,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a774a1_core_clks[] = {
+static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -121,7 +121,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
        DEF_BASE("r",           R8A774A1_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
-static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A774A1_CLK_S0D6),
        DEF_MOD("tmu3",                  122,   R8A774A1_CLK_S3D2),
        DEF_MOD("tmu2",                  123,   R8A774A1_CLK_S3D2),
@@ -276,7 +276,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
                                         (((md) & BIT(19)) >> 18) | \
                                         (((md) & BIT(17)) >> 17))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            192,    1,      128,    1,      16,     },

diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index b5927c7892c491043d1a504a62d155202c74b848..60f4f1da51962142ee50aeb122abc8a9bf477cc4 100644 (file)
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -46,7 +46,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a774b1_core_clks[] = {
+static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -118,7 +118,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
        DEF_BASE("r",           R8A774B1_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
-static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A774B1_CLK_S0D6),
        DEF_MOD("tmu3",                  122,   R8A774B1_CLK_S3D2),
        DEF_MOD("tmu2",                  123,   R8A774B1_CLK_S3D2),
@@ -272,7 +272,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
                                         (((md) & BIT(19)) >> 18) | \
                                         (((md) & BIT(17)) >> 17))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            192,    1,      128,    1,      16,     },

diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 802a9c0b1191d7bece5dad6769b2f9e2dae2bc9c..4768ceb0fa6656eb828251f1382405b95248cc39 100644 (file)
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a774c0_core_clks[] = {
+static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -131,7 +131,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
        DEF_GEN3_RCKSEL("r",   R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
 };
 
-static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
+static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A774C0_CLK_S0D6C),
        DEF_MOD("tmu3",                  122,   R8A774C0_CLK_S3D2C),
        DEF_MOD("tmu2",                  123,   R8A774C0_CLK_S3D2C),
@@ -259,7 +259,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)       (((md) & BIT(19)) >> 19)
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
        { 1,            100,    3,      100,    3,      },
        { 1,            100,    3,       58,    3,      },

diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index 617fa769dcfa38487fd60bf5f7d9c97782913bdb..28d8a8832aefd6a7cb80ae4e3df98edce81cbd80 100644 (file)
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -48,7 +48,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a774e1_core_clks[] = {
+static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = {
        DEF_BASE("r",           R8A774E1_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
-static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
        DEF_MOD("fdp1-1",                118,   R8A774E1_CLK_S0D1),
        DEF_MOD("fdp1-0",                119,   R8A774E1_CLK_S0D1),
        DEF_MOD("tmu4",                  121,   R8A774E1_CLK_S0D6),
@@ -286,7 +286,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
                                         (((md) & BIT(19)) >> 18) | \
                                         (((md) & BIT(17)) >> 17))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            192,    1,      128,    1,      16,     },

diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 1f3477fa6e5124990fe78e771dc25901bfd2570e..686f2af0052fb902e4a892e33d1f6a6b23fb1bd1 100644 (file)
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -38,7 +38,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7790_core_clks[] = {
+static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
        DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -88,7 +88,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] = {
        DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
 };
 
-static const struct mssr_mod_clk r8a7790_mod_clks[] = {
+static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
        DEF_MOD("msiof0",                  0,   R8A7790_CLK_MP),
        DEF_MOD("vcp1",                  100,   R8A7790_CLK_ZS),
        DEF_MOD("vcp0",                  101,   R8A7790_CLK_ZS),
@@ -230,7 +230,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
                                         (((md) & BIT(13)) >> 12) | \
                                         (((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
        { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
        { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
 };

diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index fcca7be8865104f929fb8e3a88965dc3bbeaa65a..dcb0fd85c52d07cff7ab1351e3379c99a86b3a2e 100644 (file)
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -1,10 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas R8A7791 CPG MSSR driver
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on the following driver from Linux kernel:
  * r8a7791 Clock Pulse Generator / Module Standby and Software Reset
  *
  * Copyright (C) 2015-2017 Glider bvba
@@ -43,7 +38,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7791_core_clks[] = {
+static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
        DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -89,7 +84,7 @@ static const struct cpg_core_clk r8a7791_core_clks[] = {
        DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
 };
 
-static const struct mssr_mod_clk r8a7791_mod_clks[] = {
+static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
        DEF_MOD("msiof0",                  0,   R8A7791_CLK_MP),
        DEF_MOD("vcp0",                  101,   R8A7791_CLK_ZS),
        DEF_MOD("vpc0",                  103,   R8A7791_CLK_ZS),
@@ -232,7 +227,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
                                         (((md) & BIT(13)) >> 12) | \
                                         (((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
        { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
        { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
 };

diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 5b333638ac06a9f73320a8dce92676131f5f53bc..496e51aa73f21b997ac56b751ae0adbb5b0dbb27 100644 (file)
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -37,7 +37,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7792_core_clks[] = {
+static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -76,7 +76,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] = {
        DEF_FIXED("osc",    R8A7792_CLK_OSC,   CLK_PLL1,      12288, 1),
 };
 
-static const struct mssr_mod_clk r8a7792_mod_clks[] = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
        DEF_MOD("msiof0",                  0,   R8A7792_CLK_MP),
        DEF_MOD("jpu",                   106,   R8A7792_CLK_M2),
        DEF_MOD("tmu1",                  111,   R8A7792_CLK_P),
@@ -174,7 +174,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
                                         (((md) & BIT(13)) >> 12) | \
                                         (((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
        { 1, 208, 106, 200 },
        { 1, 208,  88, 200 },
        { 1, 156,  80, 150 },

diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index b9dd88de98ea2a44c054c380ab50dd15c8b3b507..f1828a6e5431b6a60dfcf8e4950d984d65f097ea 100644 (file)
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -38,7 +38,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7794_core_clks[] = {
+static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
        DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -83,7 +83,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] = {
        DEF_DIV6P1("mmc0",  R8A7794_CLK_MMC0,  CLK_PLL1_DIV2, 0x240),
 };
 
-static const struct mssr_mod_clk r8a7794_mod_clks[] = {
+static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
        DEF_MOD("msiof0",                  0,   R8A7794_CLK_MP),
        DEF_MOD("vcp0",                  101,   R8A7794_CLK_ZS),
        DEF_MOD("vpc0",                  103,   R8A7794_CLK_ZS),
@@ -205,7 +205,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
                                         (((md) & BIT(13)) >> 13))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
        { 1, 208,  88, 200 },
        { 1, 156,  66, 150 },
        { 2, 240, 102, 230 },

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 005f6a9ecd7e72f715e2d4fa01068fec92e33991..0e9b9ccf979cdb236ed799dafcfe6bdf09529b33 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -50,7 +50,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7795_core_clks[] = {
+static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -126,8 +126,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
        DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
-static const struct mssr_mod_clk r8a7795_mod_clks[] = {
-       DEF_MOD("fdp1-2",                117,   R8A7795_CLK_S2D1), /* ES1.x */
+static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
        DEF_MOD("fdp1-1",                118,   R8A7795_CLK_S0D1),
        DEF_MOD("fdp1-0",                119,   R8A7795_CLK_S0D1),
        DEF_MOD("tmu4",                  121,   R8A7795_CLK_S0D6),
@@ -161,7 +160,6 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("pcie1",                 318,   R8A7795_CLK_S3D1),
        DEF_MOD("pcie0",                 319,   R8A7795_CLK_S3D1),
        DEF_MOD("usb-dmac30",            326,   R8A7795_CLK_S3D1),
-       DEF_MOD("usb3-if1",              327,   R8A7795_CLK_S3D1), /* ES1.x */
        DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
        DEF_MOD("usb-dmac31",            329,   R8A7795_CLK_S3D1),
        DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
@@ -186,28 +184,21 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
        DEF_MOD("thermal",               522,   R8A7795_CLK_CP),
        DEF_MOD("pwm",                   523,   R8A7795_CLK_S0D12),
-       DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S0D2),
        DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S0D2),
        DEF_MOD("fcpvd0",                603,   R8A7795_CLK_S0D2),
        DEF_MOD("fcpvb1",                606,   R8A7795_CLK_S0D1),
        DEF_MOD("fcpvb0",                607,   R8A7795_CLK_S0D1),
-       DEF_MOD("fcpvi2",                609,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("fcpvi1",                610,   R8A7795_CLK_S0D1),
        DEF_MOD("fcpvi0",                611,   R8A7795_CLK_S0D1),
-       DEF_MOD("fcpf2",                 613,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("fcpf1",                 614,   R8A7795_CLK_S0D1),
        DEF_MOD("fcpf0",                 615,   R8A7795_CLK_S0D1),
-       DEF_MOD("fcpci1",                616,   R8A7795_CLK_S2D1), /* ES1.x */
-       DEF_MOD("fcpci0",                617,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("fcpcs",                 619,   R8A7795_CLK_S0D1),
-       DEF_MOD("vspd3",                 620,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("vspd2",                 621,   R8A7795_CLK_S0D2),
        DEF_MOD("vspd1",                 622,   R8A7795_CLK_S0D2),
        DEF_MOD("vspd0",                 623,   R8A7795_CLK_S0D2),
        DEF_MOD("vspbc",                 624,   R8A7795_CLK_S0D1),
        DEF_MOD("vspbd",                 626,   R8A7795_CLK_S0D1),
-       DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
        DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D2),
@@ -220,7 +211,6 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("cmm2",                  709,   R8A7795_CLK_S2D1),
        DEF_MOD("cmm1",                  710,   R8A7795_CLK_S2D1),
        DEF_MOD("cmm0",                  711,   R8A7795_CLK_S2D1),
-       DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0), /* ES1.x */
        DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
        DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
        DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
@@ -324,7 +314,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
                                         (((md) & BIT(19)) >> 18) | \
                                         (((md) & BIT(17)) >> 17))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            192,    1,      128,    1,      16,     },

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 27cf62e02133732b5055324fd972a8dfe26c5822..ea1f6d69062483d593268b5360f20c1886c3fe3d 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7796_core_clks[] = {
+static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -128,7 +128,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
        DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
-static const struct mssr_mod_clk r8a7796_mod_clks[] = {
+static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
        DEF_MOD("fdp1-0",                119,   R8A7796_CLK_S0D1),
        DEF_MOD("tmu4",                  121,   R8A7796_CLK_S0D6),
        DEF_MOD("tmu3",                  122,   R8A7796_CLK_S3D2),
@@ -299,7 +299,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
                                         (((md) & BIT(19)) >> 18) | \
                                         (((md) & BIT(17)) >> 17))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            192,    1,      128,    1,      16,     },

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 58e557a95f5a02aca3e7329dbf9402aec08e276e..8a5c1525ece6fa3f4c675349bf52740ff8399373 100644 (file)
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -50,7 +50,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a77965_core_clks[] = {
+static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -124,7 +124,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
        DEF_BASE("r",           R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
-static const struct mssr_mod_clk r8a77965_mod_clks[] = {
+static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
        DEF_MOD("fdp1-0",               119,    R8A77965_CLK_S0D1),
        DEF_MOD("tmu4",                 121,    R8A77965_CLK_S0D6),
        DEF_MOD("tmu3",                 122,    R8A77965_CLK_S3D2),
@@ -302,7 +302,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
                                         (((md) & BIT(19)) >> 18) | \
                                         (((md) & BIT(17)) >> 17))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            192,    1,      128,    1,      16,     },

diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index f5d77df42335365b13ec4586506bf63fd730ca1f..32923b423fe3cd79acf366ef1f1127a2b6ee4920 100644 (file)
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -1,13 +1,12 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas R8A77970 CPG MSSR driver
+ * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
  *
- * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2017-2018 Cogent Embedded Inc.
  *
- * Based on the following driver from Linux kernel:
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ * Based on r8a7795-cpg-mssr.c
  *
- * Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2015 Glider bvba
  */
 
 #include <common.h>
@@ -42,7 +41,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a77970_core_clks[] = {
+static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -57,6 +56,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = {
        DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,  CLK_PLL1_DIV2,  2, 1),
 
        /* Core Clock Outputs */
+       DEF_FIXED("z2",         R8A77970_CLK_Z2,    CLK_PLL1_DIV4,  1, 1),
        DEF_FIXED("ztr",        R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -87,7 +87,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = {
        DEF_FIXED("r",          R8A77970_CLK_R,     CLK_EXTALR,    1, 1),
 };
 
-static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A77970_CLK_S2D2),
        DEF_MOD("tmu3",                  122,   R8A77970_CLK_S2D2),
        DEF_MOD("tmu2",                  123,   R8A77970_CLK_S2D2),
@@ -166,7 +166,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
                                         (((md) & BIT(13)) >> 12) | \
                                         (((md) & BIT(19)) >> 19))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
        { 1,            192,    1,      96,     1,      },
        { 1,            192,    1,      80,     1,      },

diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index f29727ddb90ba1cc7dd14c796bd37bafcec942f9..f35032b95f1645b21205df031a58394f5b2cfce2 100644 (file)
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -47,7 +47,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a77980_core_clks[] = {
+static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",  CLK_EXTAL),
        DEF_INPUT("extalr", CLK_EXTALR),
@@ -71,6 +71,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
        DEF_RATE(".oco",        CLK_OCO,           32768),
 
        /* Core Clock Outputs */
+       DEF_FIXED("z2",         R8A77980_CLK_Z2,    CLK_PLL2,       4, 1),
        DEF_FIXED("ztr",        R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A77980_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -110,7 +111,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
        DEF_GEN3_MDSEL("r",     R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 };
 
-static const struct mssr_mod_clk r8a77980_mod_clks[] = {
+static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A77980_CLK_S0D6),
        DEF_MOD("tmu3",                  122,   R8A77980_CLK_S0D6),
        DEF_MOD("tmu2",                  123,   R8A77980_CLK_S0D6),
@@ -149,11 +150,27 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] = {
        DEF_MOD("imp-ocv3",              529,   R8A77980_CLK_S1D1),
        DEF_MOD("imp-ocv2",              531,   R8A77980_CLK_S1D1),
        DEF_MOD("fcpvd0",                603,   R8A77980_CLK_S3D1),
+       DEF_MOD("vin15",                 604,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin14",                 605,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin13",                 608,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin12",                 612,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin11",                 618,   R8A77980_CLK_S2D1),
        DEF_MOD("vspd0",                 623,   R8A77980_CLK_S3D1),
+       DEF_MOD("vin10",                 625,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin9",                  627,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin8",                  628,   R8A77980_CLK_S2D1),
        DEF_MOD("csi41",                 715,   R8A77980_CLK_CSI0),
        DEF_MOD("csi40",                 716,   R8A77980_CLK_CSI0),
        DEF_MOD("du0",                   724,   R8A77980_CLK_S2D1),
        DEF_MOD("lvds",                  727,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin7",                  804,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin6",                  805,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin5",                  806,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin4",                  807,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin3",                  808,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin2",                  809,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin1",                  810,   R8A77980_CLK_S2D1),
+       DEF_MOD("vin0",                  811,   R8A77980_CLK_S2D1),
        DEF_MOD("etheravb",              812,   R8A77980_CLK_S3D2),
        DEF_MOD("gether",                813,   R8A77980_CLK_S3D2),
        DEF_MOD("imp3",                  824,   R8A77980_CLK_S1D1),
@@ -172,6 +189,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] = {
        DEF_MOD("gpio0",                 912,   R8A77980_CLK_CP),
        DEF_MOD("can-fd",                914,   R8A77980_CLK_S3D2),
        DEF_MOD("rpc-if",                917,   R8A77980_CLK_RPCD2),
+       DEF_MOD("i2c5",                  919,   R8A77980_CLK_S0D6),
        DEF_MOD("i2c4",                  927,   R8A77980_CLK_S0D6),
        DEF_MOD("i2c3",                  928,   R8A77980_CLK_S0D6),
        DEF_MOD("i2c2",                  929,   R8A77980_CLK_S3D2),
@@ -195,7 +213,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] = {
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
                                         (((md) & BIT(13)) >> 13))
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
        { 1,            192,    1,      192,    1,      16,     },
        { 1,            160,    1,      160,    1,      19,     },

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 1864af30c8c2ae08a2b57d339ed7e0717b363a9e..e5710b0593377aefe9b5823e43b22e96e29df6da 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a77990_core_clks[] = {
+static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -132,7 +132,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        DEF_GEN3_RCKSEL("r",   R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
 };
 
-static const struct mssr_mod_clk r8a77990_mod_clks[] = {
+static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A77990_CLK_S0D6C),
        DEF_MOD("tmu3",                  122,   R8A77990_CLK_S3D2C),
        DEF_MOD("tmu2",                  123,   R8A77990_CLK_S3D2C),
@@ -273,7 +273,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)       (((md) & BIT(19)) >> 19)
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
        { 1,            100,    3,      100,    3,      },
        { 1,            100,    3,       58,    3,      },

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 03ae863c8bc6ca2434e315abbc83d4ce40c20aee..0ef1c1d8143823be3f496478e427f756f5213dda 100644 (file)
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -50,7 +50,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a77995_core_clks[] = {
+static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -118,7 +118,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
        DEF_GEN3_RCKSEL("r",   R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
 };
 
-static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
        DEF_MOD("tmu4",                  121,   R8A77995_CLK_S1D4C),
        DEF_MOD("tmu3",                  122,   R8A77995_CLK_S3D2C),
        DEF_MOD("tmu2",                  123,   R8A77995_CLK_S3D2C),
@@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
        DEF_MOD("du0",                   724,   R8A77995_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77995_CLK_S2D1),
        DEF_MOD("mlp",                   802,   R8A77995_CLK_S2D1),
-       DEF_MOD("vin4",                  807,   R8A77995_CLK_S1D2),
+       DEF_MOD("vin4",                  807,   R8A77995_CLK_S3D1),
        DEF_MOD("etheravb",              812,   R8A77995_CLK_S3D2),
        DEF_MOD("imr0",                  823,   R8A77995_CLK_S1D2),
        DEF_MOD("gpio6",                 906,   R8A77995_CLK_S3D4),
@@ -209,7 +209,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)       (((md) & BIT(19)) >> 19)
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
        { 1,            100,    3,      100,    3,      },
        { 1,            100,    3,      58,     3,      },

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 6b7ec36ab0564d3905fcd6a42b45c14a49c34dd9..652bfe4f6d3b5d9ccc6110571d6b3754f78d08bd 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -56,7 +56,7 @@ enum clk_ids {
        DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
                 .offset = _offset)
 
-static const struct cpg_core_clk r8a779a0_core_clks[] = {
+static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",  CLK_EXTAL),
        DEF_INPUT("extalr", CLK_EXTALR),
@@ -127,7 +127,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
        DEF_GEN4_MDSEL("r",     R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 };
 
-static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("avb0",         211,    R8A779A0_CLK_S3D2),
        DEF_MOD("avb1",         212,    R8A779A0_CLK_S3D2),
        DEF_MOD("avb2",         213,    R8A779A0_CLK_S3D2),
@@ -165,14 +165,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
        DEF_MOD("msi3",         621,    R8A779A0_CLK_MSO),
        DEF_MOD("msi4",         622,    R8A779A0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779A0_CLK_MSO),
+       DEF_MOD("pwm0",         628,    R8A779A0_CLK_S1D8),
        DEF_MOD("rpc-if",       629,    R8A779A0_CLK_RPCD2),
        DEF_MOD("scif0",        702,    R8A779A0_CLK_S1D8),
        DEF_MOD("scif1",        703,    R8A779A0_CLK_S1D8),
        DEF_MOD("scif3",        704,    R8A779A0_CLK_S1D8),
        DEF_MOD("scif4",        705,    R8A779A0_CLK_S1D8),
        DEF_MOD("sdhi0",        706,    R8A779A0_CLK_SD0),
-       DEF_MOD("sydm1",        709,    R8A779A0_CLK_S1D2),
-       DEF_MOD("sydm2",        710,    R8A779A0_CLK_S1D2),
+       DEF_MOD("sys-dmac1",    709,    R8A779A0_CLK_S1D2),
+       DEF_MOD("sys-dmac2",    710,    R8A779A0_CLK_S1D2),
        DEF_MOD("tmu0",         713,    R8A779A0_CLK_CL16MCK),
        DEF_MOD("tmu1",         714,    R8A779A0_CLK_S1D4),
        DEF_MOD("tmu2",         715,    R8A779A0_CLK_S1D4),

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 7aac28ed4963bf717781ac8dae7289c2f55103ff..643e8b8da9763af92f5f16c8fca23d25362936c7 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -47,7 +47,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a779f0_core_clks[] = {
+static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] = {
        DEF_GEN4_MDSEL("r",     R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 };
 
-static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
        DEF_MOD("hscif0",       514,    R8A779F0_CLK_SASYNCPERD1),
        DEF_MOD("hscif1",       515,    R8A779F0_CLK_SASYNCPERD1),
        DEF_MOD("hscif2",       516,    R8A779F0_CLK_SASYNCPERD1),

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 8625e8a2d36e291768ba45e40db2e37a745f837a..219024a7416e2c98fe9fb215b220ad313526e46b 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -56,7 +56,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a779g0_core_clks[] = {
+static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -142,6 +142,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] = {
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
        DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
        DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
+       DEF_DIV6P1("csi",       R8A779G0_CLK_CSI,       CLK_PLL5_DIV4,  0x880),
        DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
        DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
 
@@ -156,11 +157,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] = {
        DEF_GEN4_MDSEL("r",     R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 };
 
-static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb1",         212,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb2",         213,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("canfd0",       328,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("csi40",        331,    R8A779G0_CLK_CSI),
+       DEF_MOD("csi41",        400,    R8A779G0_CLK_CSI),
        DEF_MOD("dis0",         411,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("dsitxlink0",   415,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("dsitxlink1",   416,    R8A779G0_CLK_VIOBUSD2),
@@ -177,6 +180,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
        DEF_MOD("i2c4",         522,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("i2c5",         523,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("irqc",         611,    R8A779G0_CLK_CL16M),
+       DEF_MOD("ispcs0",       612,    R8A779G0_CLK_S0D2_VIO),
+       DEF_MOD("ispcs1",       613,    R8A779G0_CLK_S0D2_VIO),
        DEF_MOD("msi0",         618,    R8A779G0_CLK_MSO),
        DEF_MOD("msi1",         619,    R8A779G0_CLK_MSO),
        DEF_MOD("msi2",         620,    R8A779G0_CLK_MSO),
@@ -198,6 +203,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
        DEF_MOD("tmu3",         716,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tmu4",         717,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("vin00",        730,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin01",        731,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin02",        800,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin03",        801,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin04",        802,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin05",        803,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin06",        804,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin07",        805,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin10",        806,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin11",        807,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin12",        808,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin13",        809,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin14",        810,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin15",        811,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin16",        812,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin17",        813,    R8A779G0_CLK_S0D4_VIO),
        DEF_MOD("vspd0",        830,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("vspd1",        831,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),
@@ -209,6 +230,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
        DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc3",         918,    R8A779G0_CLK_CL16M),
+       DEF_MOD("tsc",          919,    R8A779G0_CLK_CL16M),
+       DEF_MOD("ssiu",         2926,   R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("ssi",          2927,   R8A779G0_CLK_S0D6_PER),
 };
 
 /*

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0ea39b4a3f11aa623bc5d3735874349e34a73e79..32f44e5bbd7dac7ac602236a6bc52cbb24fc4ad0 100644 (file)
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -131,7 +131,7 @@ config PINCTRL_PFC_R8A779G0
        help
          Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
 
-config PINCTRL_PFC_R7S72100
+config PINCTRL_RZA1
        bool "Renesas RZ/A1 R7S72100 pin control driver"
        depends on CPU_RZA1
        default y if CPU_RZA1

diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1a61c39d8471ad6722d203564688ff6b7b5104d2..f9a68794eb9c60b6cd72afc257e715f6b317ea2b 100644 (file)
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -2,13 +2,13 @@ obj-$(CONFIG_PINCTRL_PFC) += pfc.o
 obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
 obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
-obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a77951.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
@@ -19,5 +19,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
 obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
 obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
-obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
 obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o

diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 432895ac55c2c7f321c5377c8a55054089bfef7f..7203648bbc80d6f65effeb03194764aff014a7ee 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -24,7 +24,7 @@
        PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
        PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
        PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
-       PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),   \
        PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
        PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
 
@@ -5824,7 +5824,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_I2C1 [2] */
                FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)

diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index 219333106fc6eafceffe4820530bca1d21413428..b25453ed28521fe7f1aed19878012bf685b3db47 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -25,7 +25,7 @@
        PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
        PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
        PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
-       PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),   \
        PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
        PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
        PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
@@ -6555,7 +6555,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
                /* RESERVED [6] */ ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6877,7 +6877,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 81cfe81c7f549ac630b34a91b90781997480c9d4..08f1f97af6efc0e4b94581eea01b39bafe6af5ac 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -2629,7 +2629,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP7_1_0 [2] */
                FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c
index 7ed54f0cfff706587a8bcb324ac7246f828cef9e..e5d125ceca0caba854c8921c09f54fe62bcc7994 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7794.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
@@ -43,30 +43,30 @@
        PORT_GP_1(5, 25, fn, sfx),                                      \
        PORT_GP_1(5, 26, fn, sfx),                                      \
        PORT_GP_1(5, 27, fn, sfx),                                      \
-       PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),        \
-       PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),        \
-       PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),       \
-       PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),       \
-       PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
-       PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP),      \
+       PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),  \
+       PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),  \
+       PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+       PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
+       PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),        \
        PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
        PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
 
@@ -5513,7 +5513,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_SSI9_0, FN_SEL_SSI9_1,
                /* RESERVED [12] */ ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)

diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
similarity index 99%
rename from drivers/pinctrl/renesas/pfc-r8a7795.c
rename to drivers/pinctrl/renesas/pfc-r8a77951.c
index d094bd7cc9466c33b6bc37e91b6fdc9baab9f689..5d1c81c3eae5720596a635034e8d879bab2a86cd 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -19,12 +19,12 @@
        PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
-       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
+       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
        PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
-       PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
+       PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
        PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5612,7 +5612,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED 16-1 */
                MOD_SEL2_0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5863,7 +5863,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30/USB2_CH3_PWEN */
                { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31/USB2_CH3_OVC */
        } },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -5874,7 +5874,7 @@ enum ioctrl_regs {
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6131,7 +6131,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 3cc4a3b366a42245496fbc1da9b20ecd637955c8..163d1805dfb449dfb4950b8209fdf2191d7ae69e 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -25,12 +25,12 @@
        PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
-       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
+       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
        PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
-       PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
+       PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
        PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5568,7 +5568,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED 16-1 */
                MOD_SEL2_0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5816,7 +5816,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
                { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
        } },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -5827,7 +5827,7 @@ enum ioctrl_regs {
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6084,7 +6084,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 04e8371f51ef44b4a015a8660e6b7aa796962a43..377143d391834a67ab1989a93221f109e13fc452 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -26,12 +26,12 @@
        PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
-       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
+       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
        PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
        PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
-       PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
+       PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
        PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
        PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5809,7 +5809,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED 16-1 */
                MOD_SEL2_0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -6057,7 +6057,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
                { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
        } },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -6068,7 +6068,7 @@ enum ioctrl_regs {
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6325,7 +6325,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 04f0345233642f36d89e7eb7dbe45826df47f4d6..1cc6fa4f3fc5cdfd3643d4239576a5ecc37380cd 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -21,10 +21,10 @@
 #include "sh_pfc.h"
 
 #define CPU_ALL_GP(fn, sfx)                                            \
-       PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
+       PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
-       PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
-       PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
+       PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
+       PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PORT_GP_CFG_6(4,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
 
@@ -36,7 +36,8 @@
        PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
-       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP),      \
+       PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
 
 /*
  * F_() : just information
@@ -172,7 +173,7 @@
 #define IP0_31_28      FM(DU_DG3)                      FM(MSIOF3_SS2)          F_(0, 0)        FM(A7)          FM(PWMFSW0)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0                FM(DU_DG4)                      F_(0, 0)                F_(0, 0)        FM(A8)          FM(FSO_CFE_0_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4                FM(DU_DG5)                      F_(0, 0)                F_(0, 0)        FM(A9)          FM(FSO_CFE_1_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8       FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8       FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_15_12      FM(DU_DG7)                      F_(0, 0)                F_(0, 0)        FM(A11)         FM(IRQ1)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_19_16      FM(DU_DB2)                      F_(0, 0)                F_(0, 0)        FM(A12)         FM(IRQ2)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_23_20      FM(DU_DB3)                      F_(0, 0)                F_(0, 0)        FM(A13)         FM(FXR_CLKOUT1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -2344,7 +2345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL0_1
                MOD_SEL0_0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -2359,26 +2360,37 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL1] = { 0xe6060384 },
        [POCCTRL2] = { 0xe6060388 },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
        int bit = pin & 0x1f;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
-       if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+       switch (pin) {
+       case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
                return bit;
-       if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+       case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
                return bit + 22;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
-       if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+       case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
                return bit - 10;
-       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+
+       case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
                return bit + 7;
 
-       return -EINVAL;
+       case PIN_VDDQ_AVB0:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+               return 0;
+
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index 19bd46c9e48cb6e4217d3b8913d07e09e808657e..523faa0ac8f66efa915d24584828f62ee4bbd1ee 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -21,10 +21,10 @@
 #include "sh_pfc.h"
 
 #define CPU_ALL_GP(fn, sfx)    \
-       PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
+       PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
-       PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
-       PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+       PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
+       PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
        PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
 
@@ -37,7 +37,9 @@
        PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),   \
-       PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+       PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+       PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
+       PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
 
 /*
  * F_() : just information
@@ -99,7 +101,7 @@
 #define GPSR1_0                F_(IRQ0,                IP2_27_24)
 
 /* GPSR2 */
-#define GPSR2_29       F_(FSO_TOE_N,           IP10_19_16)
+#define GPSR2_29       F_(FSO_TOE_N,           IP10_19_16)
 #define GPSR2_28       F_(FSO_CFE_1_N,         IP10_15_12)
 #define GPSR2_27       F_(FSO_CFE_0_N,         IP10_11_8)
 #define GPSR2_26       F_(SDA3,                IP10_7_4)
@@ -264,11 +266,11 @@
 #define IP8_11_8       FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)              FM(DU_CDE)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_15_12      FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)              FM(TCLK1_B)     FM(TX1_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_19_16      FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)              FM(TCLK2_B)     FM(RX1_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20      FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)              FM(SPEEDIN_B)   FM(SCIF_CLK_B)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20      FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)              FM(SPEEDIN_B)   FM(SCIF_CLK_B)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_27_24      FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_31_28      FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_3_0                FM(IRQ4)                        F_(0, 0)                F_(0, 0)                FM(VI0_DATA12)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4        FM(IRQ5)                        F_(0, 0)                F_(0, 0)                FM(VI0_DATA13)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4                FM(IRQ5)                        F_(0, 0)                F_(0, 0)                FM(VI0_DATA13)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_11_8       FM(MSIOF0_RXD)                  FM(DU_DR0)              F_(0, 0)                FM(VI0_DATA14)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_15_12      FM(MSIOF0_TXD)                  FM(DU_DR1)              F_(0, 0)                FM(VI0_DATA15)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_19_16      FM(MSIOF0_SCK)                  FM(DU_DG0)              F_(0, 0)                FM(VI0_DATA16)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -2815,7 +2817,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL0_1
                MOD_SEL0_0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -2832,31 +2834,46 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL2] = { 0xe6060388, },
        [POCCTRL3] = { 0xe606038c, },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
        int bit = pin & 0x1f;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
-       if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+       switch (pin) {
+       case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
                return bit;
-       else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+       case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
                return bit + 22;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
-       if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+       case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
                return bit - 10;
-       if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
-           (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
+
+       case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
+       case RCAR_GP_PIN(3,  0) ... RCAR_GP_PIN(3, 16):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
                return bit + 7;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
-       if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+       case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
                return pin - 25;
 
-       return -EINVAL;
+       case PIN_VDDQ_AVB:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+               return 0;
+
+       case PIN_VDDQ_GE:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+               return 1;
+
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index c6c3d0988b0ff792fc024f06b1bc97ae31d2a403..215a19ef9cdc305ccd2057664286a5647d674861 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -26,12 +26,12 @@
        PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
-       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+       PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
        PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
-       PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+       PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
        PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -60,7 +60,8 @@
        PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
-       PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
+       PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP),     \
+       PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
 
 /*
  * F_() : just information
@@ -511,7 +512,8 @@ MOD_SEL0_1_0
        FM(AVB_TD3) \
        FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
        FM(ASEBRK) \
-       FM(MLB_REF)
+       FM(MLB_REF) \
+       FM(VDDQ_AVB0)
 
 enum {
        PINMUX_RESERVED = 0,
@@ -5006,7 +5008,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL1_4
                /* RESERVED 3, 2, 1, 0  */ ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5039,33 +5041,40 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(4,  9), 17, 2 },  /* SD3_DAT7 */
                { RCAR_GP_PIN(4, 10), 14, 2 },  /* SD3_DS */
        } },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
        POCCTRL0,
+       POCCTRL2,
        TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL0] = { 0xe6060380, },
+       [POCCTRL2] = { 0xe6060388, },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
-       int bit = -EINVAL;
+       switch (pin) {
+       case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+               return pin & 0x1f;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+       case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+               return (pin & 0x1f) + 19;
 
-       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
-               bit = pin & 0x1f;
+       case PIN_VDDQ_AVB0:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+               return 0;
 
-       if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
-               bit = (pin & 0x1f) + 19;
-
-       return bit;
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -5273,7 +5282,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = RCAR_GP_PIN(6,  9),      /* USB30_OVC */
                [31] = RCAR_GP_PIN(6, 17),      /* USB30_PWEN */
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 06caf16c991820c24ba9feb7044863b6e607caa8..c0d69937ddb4dbd2fcf8152e4184c901f9a58c29 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -23,7 +23,7 @@
        PORT_GP_CFG_9(0,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
-       PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
+       PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
        PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
-       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP),      \
+       PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
 
 /*
  * F_() : just information
@@ -2854,19 +2855,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL1_26
                /* RESERVED 25-0 */ ))
        },
-       { },
+       { /* sentinel */ }
+};
+
+enum ioctrl_regs {
+       POCCTRL0,
+       POCCTRL2,
+       TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+       [POCCTRL0] = { 0xe6060380, },
+       [POCCTRL2] = { 0xe6060388, },
+       [TDSELCTRL] = { 0xe60603c0, },
+       { /* sentinel */ }
 };
 
+
 static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
-       int bit = -EINVAL;
-
-       *pocctrl = 0xe6060380;
+       switch (pin) {
+       case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+               return 29 - (pin - RCAR_GP_PIN(3, 0));
 
-       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
-               bit = 29 - (pin - RCAR_GP_PIN(3, 0));
+       case PIN_VDDQ_AVB0:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+               return 0;
 
-       return bit;
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -3077,15 +3096,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
        { /* sentinel */ }
 };
 
-enum ioctrl_regs {
-       TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-       [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
-};
-
 static const struct pinmux_bias_reg *
 r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
                         unsigned int *puen_bit, unsigned int *pud_bit)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 0f570e4ea5e1caeb14e7d1cca1e46726f9ed782e..3c4b03b1b4c1bdeaf27042cbc2f20c603078d6a8 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -3633,7 +3633,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL2_3_2
                /* RESERVED 1-0 */ ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -3938,7 +3938,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(9, 17),  4, 3 },  /* AVB5_LINK */
                { RCAR_GP_PIN(9, 16),  0, 3 },  /* AVB5_PHY_INT */
        } },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -3965,7 +3965,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POC8] = { 0xe60690a0, },
        [POC9] = { 0xe60698a0, },
        [TD1SEL0] = { 0xe6058124, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -4352,7 +4352,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index e2ac9d1efde78272c62dcf19f2957ae13a03cb0b..5123e26e0acc11b47de397c0b8b1c8cf448747ec 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1216,7 +1216,7 @@ static const unsigned int tsn1_avtp_pps_pins[] = {
        RCAR_GP_PIN(3, 13),
 };
 static const unsigned int tsn1_avtp_pps_mux[] = {
-       TSN0_AVTP_PPS_MARK,
+       TSN1_AVTP_PPS_MARK,
 };
 static const unsigned int tsn1_avtp_capture_a_pins[] = {
        /* TSN1_AVTP_CAPTURE_A */
@@ -1787,7 +1787,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL1_3_2
                MOD_SEL1_1_0))
        },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -1899,7 +1899,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(3, 17),  4, 3 },  /* TSN0_AVTP_MATCH_B */
                { RCAR_GP_PIN(3, 16),  0, 3 },  /* TSN0_AVTP_PPS */
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -1914,7 +1914,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POC1] = { 0xe60508a0, },
        [POC3] = { 0xe60518a0, },
        [TD0SEL1] = { 0xe6050920, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -2073,7 +2073,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 78a91f426d97087a6554daf489ac3ba548d8abc3..20498a1c2f74b01fb89190cde99c262efcd7b053 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -52,6 +52,12 @@
        PORT_GP_CFG_21(7,       fn, sfx, CFG_FLAGS),                                    \
        PORT_GP_CFG_14(8,       fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
 
+#define CPU_ALL_NOGP(fn)                                                               \
+       PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),      \
+       PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),      \
+       PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),      \
+       PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
+
 /* GPSR0 */
 #define GPSR0_18       F_(MSIOF2_RXD,          IP2SR0_11_8)
 #define GPSR0_17       F_(MSIOF2_SCK,          IP2SR0_7_4)
@@ -159,54 +165,54 @@
 #define GPSR3_0                F_(MMC_SD_D1,           IP0SR3_3_0)
 
 /* GPSR4 */
-#define GPSR4_24       FM(AVS1)
-#define GPSR4_23       FM(AVS0)
-#define GPSR4_22       FM(PCIE1_CLKREQ_N)
-#define GPSR4_21       FM(PCIE0_CLKREQ_N)
-#define GPSR4_20       FM(TSN0_TXCREFCLK)
-#define GPSR4_19       FM(TSN0_TD2)
-#define GPSR4_18       FM(TSN0_TD3)
-#define GPSR4_17       FM(TSN0_RD2)
-#define GPSR4_16       FM(TSN0_RD3)
-#define GPSR4_15       FM(TSN0_TD0)
-#define GPSR4_14       FM(TSN0_TD1)
-#define GPSR4_13       FM(TSN0_RD1)
-#define GPSR4_12       FM(TSN0_TXC)
-#define GPSR4_11       FM(TSN0_RXC)
-#define GPSR4_10       FM(TSN0_RD0)
-#define GPSR4_9                FM(TSN0_TX_CTL)
-#define GPSR4_8                FM(TSN0_AVTP_PPS0)
-#define GPSR4_7                FM(TSN0_RX_CTL)
-#define GPSR4_6                FM(TSN0_AVTP_CAPTURE)
-#define GPSR4_5                FM(TSN0_AVTP_MATCH)
-#define GPSR4_4                FM(TSN0_LINK)
-#define GPSR4_3                FM(TSN0_PHY_INT)
-#define GPSR4_2                FM(TSN0_AVTP_PPS1)
-#define GPSR4_1                FM(TSN0_MDC)
-#define GPSR4_0                FM(TSN0_MDIO)
+#define GPSR4_24       F_(AVS1,                IP3SR4_3_0)
+#define GPSR4_23       F_(AVS0,                IP2SR4_31_28)
+#define GPSR4_22       F_(PCIE1_CLKREQ_N,      IP2SR4_27_24)
+#define GPSR4_21       F_(PCIE0_CLKREQ_N,      IP2SR4_23_20)
+#define GPSR4_20       F_(TSN0_TXCREFCLK,      IP2SR4_19_16)
+#define GPSR4_19       F_(TSN0_TD2,            IP2SR4_15_12)
+#define GPSR4_18       F_(TSN0_TD3,            IP2SR4_11_8)
+#define GPSR4_17       F_(TSN0_RD2,            IP2SR4_7_4)
+#define GPSR4_16       F_(TSN0_RD3,            IP2SR4_3_0)
+#define GPSR4_15       F_(TSN0_TD0,            IP1SR4_31_28)
+#define GPSR4_14       F_(TSN0_TD1,            IP1SR4_27_24)
+#define GPSR4_13       F_(TSN0_RD1,            IP1SR4_23_20)
+#define GPSR4_12       F_(TSN0_TXC,            IP1SR4_19_16)
+#define GPSR4_11       F_(TSN0_RXC,            IP1SR4_15_12)
+#define GPSR4_10       F_(TSN0_RD0,            IP1SR4_11_8)
+#define GPSR4_9                F_(TSN0_TX_CTL,         IP1SR4_7_4)
+#define GPSR4_8                F_(TSN0_AVTP_PPS0,      IP1SR4_3_0)
+#define GPSR4_7                F_(TSN0_RX_CTL,         IP0SR4_31_28)
+#define GPSR4_6                F_(TSN0_AVTP_CAPTURE,   IP0SR4_27_24)
+#define GPSR4_5                F_(TSN0_AVTP_MATCH,     IP0SR4_23_20)
+#define GPSR4_4                F_(TSN0_LINK,           IP0SR4_19_16)
+#define GPSR4_3                F_(TSN0_PHY_INT,        IP0SR4_15_12)
+#define GPSR4_2                F_(TSN0_AVTP_PPS1,      IP0SR4_11_8)
+#define GPSR4_1                F_(TSN0_MDC,            IP0SR4_7_4)
+#define GPSR4_0                F_(TSN0_MDIO,           IP0SR4_3_0)
 
 /* GPSR 5 */
-#define GPSR5_20       FM(AVB2_RX_CTL)
-#define GPSR5_19       FM(AVB2_TX_CTL)
-#define GPSR5_18       FM(AVB2_RXC)
-#define GPSR5_17       FM(AVB2_RD0)
-#define GPSR5_16       FM(AVB2_TXC)
-#define GPSR5_15       FM(AVB2_TD0)
-#define GPSR5_14       FM(AVB2_RD1)
-#define GPSR5_13       FM(AVB2_RD2)
-#define GPSR5_12       FM(AVB2_TD1)
-#define GPSR5_11       FM(AVB2_TD2)
-#define GPSR5_10       FM(AVB2_MDIO)
-#define GPSR5_9                FM(AVB2_RD3)
-#define GPSR5_8                FM(AVB2_TD3)
-#define GPSR5_7                FM(AVB2_TXCREFCLK)
-#define GPSR5_6                FM(AVB2_MDC)
-#define GPSR5_5                FM(AVB2_MAGIC)
-#define GPSR5_4                FM(AVB2_PHY_INT)
-#define GPSR5_3                FM(AVB2_LINK)
-#define GPSR5_2                FM(AVB2_AVTP_MATCH)
-#define GPSR5_1                FM(AVB2_AVTP_CAPTURE)
-#define GPSR5_0                FM(AVB2_AVTP_PPS)
+#define GPSR5_20       F_(AVB2_RX_CTL,         IP2SR5_19_16)
+#define GPSR5_19       F_(AVB2_TX_CTL,         IP2SR5_15_12)
+#define GPSR5_18       F_(AVB2_RXC,            IP2SR5_11_8)
+#define GPSR5_17       F_(AVB2_RD0,            IP2SR5_7_4)
+#define GPSR5_16       F_(AVB2_TXC,            IP2SR5_3_0)
+#define GPSR5_15       F_(AVB2_TD0,            IP1SR5_31_28)
+#define GPSR5_14       F_(AVB2_RD1,            IP1SR5_27_24)
+#define GPSR5_13       F_(AVB2_RD2,            IP1SR5_23_20)
+#define GPSR5_12       F_(AVB2_TD1,            IP1SR5_19_16)
+#define GPSR5_11       F_(AVB2_TD2,            IP1SR5_15_12)
+#define GPSR5_10       F_(AVB2_MDIO,           IP1SR5_11_8)
+#define GPSR5_9                F_(AVB2_RD3,            IP1SR5_7_4)
+#define GPSR5_8                F_(AVB2_TD3,            IP1SR5_3_0)
+#define GPSR5_7                F_(AVB2_TXCREFCLK,      IP0SR5_31_28)
+#define GPSR5_6                F_(AVB2_MDC,            IP0SR5_27_24)
+#define GPSR5_5                F_(AVB2_MAGIC,          IP0SR5_23_20)
+#define GPSR5_4                F_(AVB2_PHY_INT,        IP0SR5_19_16)
+#define GPSR5_3                F_(AVB2_LINK,           IP0SR5_15_12)
+#define GPSR5_2                F_(AVB2_AVTP_MATCH,     IP0SR5_11_8)
+#define GPSR5_1                F_(AVB2_AVTP_CAPTURE,   IP0SR5_7_4)
+#define GPSR5_0                F_(AVB2_AVTP_PPS,       IP0SR5_3_0)
 
 /* GPSR 6 */
 #define GPSR6_20       F_(AVB1_TXCREFCLK,      IP2SR6_19_16)
@@ -271,209 +277,271 @@
 #define GPSR8_0                F_(SCL0,                IP0SR8_3_0)
 
 /* SR0 */
-/* IP0SR0 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR0_3_0     F_(0, 0)                FM(ERROROUTC_B)         FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_7_4     F_(0, 0)                FM(MSIOF3_SS1)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_11_8    F_(0, 0)                FM(MSIOF3_SS2)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_15_12   FM(IRQ3)                FM(MSIOF3_SCK)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_19_16   FM(IRQ2)                FM(MSIOF3_TXD)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_23_20   FM(IRQ1)                FM(MSIOF3_RXD)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_27_24   FM(IRQ0)                FM(MSIOF3_SYNC)         F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_31_28   FM(MSIOF5_SS2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR0 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR0_3_0     FM(MSIOF5_SS1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_7_4     FM(MSIOF5_SYNC)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_11_8    FM(MSIOF5_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_15_12   FM(MSIOF5_SCK)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_19_16   FM(MSIOF5_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_23_20   FM(MSIOF2_SS2)          FM(TCLK1)               FM(IRQ2_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_27_24   FM(MSIOF2_SS1)          FM(HTX1)                FM(TX1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_31_28   FM(MSIOF2_SYNC)         FM(HRX1)                FM(RX1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP2SR0 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP2SR0_3_0     FM(MSIOF2_TXD)          FM(HCTS1_N)             FM(CTS1_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_7_4     FM(MSIOF2_SCK)          FM(HRTS1_N)             FM(RTS1_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_11_8    FM(MSIOF2_RXD)          FM(HSCK1)               FM(SCK1)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR0_3_0     F_(0, 0)                FM(ERROROUTC_N_B)       FM(TCLK2_A)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_7_4     F_(0, 0)                FM(MSIOF3_SS1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_11_8    F_(0, 0)                FM(MSIOF3_SS2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12   FM(IRQ3)                FM(MSIOF3_SCK)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16   FM(IRQ2)                FM(MSIOF3_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20   FM(IRQ1)                FM(MSIOF3_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24   FM(IRQ0)                FM(MSIOF3_SYNC)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_31_28   FM(MSIOF5_SS2)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR0_3_0     FM(MSIOF5_SS1)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_7_4     FM(MSIOF5_SYNC)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_11_8    FM(MSIOF5_TXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_15_12   FM(MSIOF5_SCK)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_19_16   FM(MSIOF5_RXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20   FM(MSIOF2_SS2)          FM(TCLK1)               FM(IRQ2_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_27_24   FM(MSIOF2_SS1)          FM(HTX1)                FM(TX1)                 F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_31_28   FM(MSIOF2_SYNC)         FM(HRX1)                FM(RX1)                 F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR0_3_0     FM(MSIOF2_TXD)          FM(HCTS1_N)             FM(CTS1_N)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_7_4     FM(MSIOF2_SCK)          FM(HRTS1_N)             FM(RTS1_N)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_11_8    FM(MSIOF2_RXD)          FM(HSCK1)               FM(SCK1)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR1 */
-/* IP0SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR1_3_0     FM(MSIOF1_SS2)          FM(HTX3_A)              FM(TX3)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_7_4     FM(MSIOF1_SS1)          FM(HCTS3_N_A)           FM(RX3)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_11_8    FM(MSIOF1_SYNC)         FM(HRTS3_N_A)           FM(RTS3_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_15_12   FM(MSIOF1_SCK)          FM(HSCK3_A)             FM(CTS3_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_19_16   FM(MSIOF1_TXD)          FM(HRX3_A)              FM(SCK3)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_23_20   FM(MSIOF1_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24   FM(MSIOF0_SS2)          FM(HTX1_X)              FM(TX1_X)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28   FM(MSIOF0_SS1)          FM(HRX1_X)              FM(RX1_X)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR1_3_0     FM(MSIOF0_SYNC)         FM(HCTS1_N_X)           FM(CTS1_N_X)    FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4     FM(MSIOF0_TXD)          FM(HRTS1_N_X)           FM(RTS1_N_X)    FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_X)             FM(SCK1_X)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_15_12   FM(MSIOF0_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_19_16   FM(HTX0)                FM(TX0)                 F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_27_24   FM(HRTS0_N)             FM(RTS0_N)              FM(PWM9_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_31_28   FM(HSCK0)               FM(SCK0)                FM(PWM0_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP2SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP2SR1_3_0     FM(HRX0)                FM(RX0)                 F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_7_4     FM(SCIF_CLK)            FM(IRQ4_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_11_8    FM(SSI_SCK)             FM(TCLK3)               F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_15_12   FM(SSI_WS)              FM(TCLK4)               F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_19_16   FM(SSI_SD)              FM(IRQ0_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_23_20   FM(AUDIO_CLKOUT)        FM(IRQ1_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_27_24   FM(AUDIO_CLKIN)         FM(PWM3_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_31_28   F_(0, 0)                FM(TCLK2)               FM(MSIOF4_SS1)  FM(IRQ3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP3SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP3SR1_3_0     FM(HRX3)                FM(SCK3_A)              FM(MSIOF4_SS2)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_7_4     FM(HSCK3)               FM(CTS3_N_A)            FM(MSIOF4_SCK)  FM(TPU0TO0_A)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_11_8    FM(HRTS3_N)             FM(RTS3_N_A)            FM(MSIOF4_TXD)  FM(TPU0TO1_A)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_15_12   FM(HCTS3_N)             FM(RX3_A)               FM(MSIOF4_RXD)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_19_16   FM(HTX3)                FM(TX3_A)               FM(MSIOF4_SYNC) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR1 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR1_3_0     FM(MSIOF1_SS2)          FM(HTX3_A)              FM(TX3)                 F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4     FM(MSIOF1_SS1)          FM(HCTS3_N_A)           FM(RX3)                 F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8    FM(MSIOF1_SYNC)         FM(HRTS3_N_A)           FM(RTS3_N)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12   FM(MSIOF1_SCK)          FM(HSCK3_A)             FM(CTS3_N)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16   FM(MSIOF1_TXD)          FM(HRX3_A)              FM(SCK3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_23_20   FM(MSIOF1_RXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24   FM(MSIOF0_SS2)          FM(HTX1_X)              FM(TX1_X)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28   FM(MSIOF0_SS1)          FM(HRX1_X)              FM(RX1_X)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR1 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR1_3_0     FM(MSIOF0_SYNC)         FM(HCTS1_N_X)           FM(CTS1_N_X)            FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4     FM(MSIOF0_TXD)          FM(HRTS1_N_X)           FM(RTS1_N_X)            FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_X)             FM(SCK1_X)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_15_12   FM(MSIOF0_RXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_19_16   FM(HTX0)                FM(TX0)                 F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24   FM(HRTS0_N)             FM(RTS0_N)              FM(PWM9_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28   FM(HSCK0)               FM(SCK0)                FM(PWM0_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR1 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR1_3_0     FM(HRX0)                FM(RX0)                 F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_7_4     FM(SCIF_CLK)            FM(IRQ4_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_11_8    FM(SSI_SCK)             FM(TCLK3)               F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_15_12   FM(SSI_WS)              FM(TCLK4)               F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16   FM(SSI_SD)              FM(IRQ0_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20   FM(AUDIO_CLKOUT)        FM(IRQ1_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_27_24   FM(AUDIO_CLKIN)         FM(PWM3_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_31_28   F_(0, 0)                FM(TCLK2)               FM(MSIOF4_SS1)          FM(IRQ3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR1 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP3SR1_3_0     FM(HRX3)                FM(SCK3_A)              FM(MSIOF4_SS2)          F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4     FM(HSCK3)               FM(CTS3_N_A)            FM(MSIOF4_SCK)          FM(TPU0TO0_A)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8    FM(HRTS3_N)             FM(RTS3_N_A)            FM(MSIOF4_TXD)          FM(TPU0TO1_A)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12   FM(HCTS3_N)             FM(RX3_A)               FM(MSIOF4_RXD)          F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16   FM(HTX3)                FM(TX3_A)               FM(MSIOF4_SYNC)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR2 */
-/* IP0SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR2_3_0     FM(FXR_TXDA)            FM(CANFD1_TX)           FM(TPU0TO2_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_7_4     FM(FXR_TXENA_N)         FM(CANFD1_RX)           FM(TPU0TO3_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_11_8    FM(RXDA_EXTFXR)         FM(CANFD5_TX)           FM(IRQ5)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_15_12   FM(CLK_EXTFXR)          FM(CANFD5_RX)           FM(IRQ4_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_19_16   FM(RXDB_EXTFXR)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_23_20   FM(FXR_TXENB_N)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_27_24   FM(FXR_TXDB)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_31_28   FM(TPU0TO1)             FM(CANFD6_TX)           F_(0, 0)        FM(TCLK2_B)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR2_3_0     FM(TPU0TO0)             FM(CANFD6_RX)           F_(0, 0)        FM(TCLK1_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_7_4     FM(CAN_CLK)             FM(FXR_TXENA_N_X)       F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_11_8    FM(CANFD0_TX)           FM(FXR_TXENB_N_X)       F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_15_12   FM(CANFD0_RX)           FM(STPWT_EXTFXR)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_19_16   FM(CANFD2_TX)           FM(TPU0TO2)             F_(0, 0)        FM(TCLK3_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_23_20   FM(CANFD2_RX)           FM(TPU0TO3)             FM(PWM1_B)      FM(TCLK4_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_27_24   FM(CANFD3_TX)           F_(0, 0)                FM(PWM2_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_31_28   FM(CANFD3_RX)           F_(0, 0)                FM(PWM3_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP2SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP2SR2_3_0     FM(CANFD4_TX)           F_(0, 0)                FM(PWM4)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_7_4     FM(CANFD4_RX)           F_(0, 0)                FM(PWM5)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_11_8    FM(CANFD7_TX)           F_(0, 0)                FM(PWM6)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_15_12   FM(CANFD7_RX)           F_(0, 0)                FM(PWM7)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR2_3_0     FM(FXR_TXDA)            FM(CANFD1_TX)           FM(TPU0TO2_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4     FM(FXR_TXENA_N)         FM(CANFD1_RX)           FM(TPU0TO3_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_11_8    FM(RXDA_EXTFXR)         FM(CANFD5_TX)           FM(IRQ5)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12   FM(CLK_EXTFXR)          FM(CANFD5_RX)           FM(IRQ4_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_19_16   FM(RXDB_EXTFXR)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_23_20   FM(FXR_TXENB_N)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_27_24   FM(FXR_TXDB)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_31_28   FM(TPU0TO1)             FM(CANFD6_TX)           F_(0, 0)                FM(TCLK2_B)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR2_3_0     FM(TPU0TO0)             FM(CANFD6_RX)           F_(0, 0)                FM(TCLK1_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4     FM(CAN_CLK)             FM(FXR_TXENA_N_X)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8    FM(CANFD0_TX)           FM(FXR_TXENB_N_X)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_15_12   FM(CANFD0_RX)           FM(STPWT_EXTFXR)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_19_16   FM(CANFD2_TX)           FM(TPU0TO2)             F_(0, 0)                FM(TCLK3_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20   FM(CANFD2_RX)           FM(TPU0TO3)             FM(PWM1_B)              FM(TCLK4_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24   FM(CANFD3_TX)           F_(0, 0)                FM(PWM2_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_31_28   FM(CANFD3_RX)           F_(0, 0)                FM(PWM3_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR2_3_0     FM(CANFD4_TX)           F_(0, 0)                FM(PWM4)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_7_4     FM(CANFD4_RX)           F_(0, 0)                FM(PWM5)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_11_8    FM(CANFD7_TX)           F_(0, 0)                FM(PWM6)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_15_12   FM(CANFD7_RX)           F_(0, 0)                FM(PWM7)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR3 */
-/* IP0SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR3_3_0     FM(MMC_SD_D1)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_7_4     FM(MMC_SD_D0)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_11_8    FM(MMC_SD_D2)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_15_12   FM(MMC_SD_CLK)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_19_16   FM(MMC_DS)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_23_20   FM(MMC_SD_D3)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_27_24   FM(MMC_D5)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_31_28   FM(MMC_D4)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR3_3_0     FM(MMC_D7)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_7_4     FM(MMC_D6)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_11_8    FM(MMC_SD_CMD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_15_12   FM(SD_CD)               F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_19_16   FM(SD_WP)               F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_23_20   FM(IPC_CLKIN)           FM(IPC_CLKEN_IN)        FM(PWM1_A)      FM(TCLK3_X)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_27_24   FM(IPC_CLKOUT)          FM(IPC_CLKEN_OUT)       FM(ERROROUTC_A) FM(TCLK4_X)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_31_28   FM(QSPI0_SSL)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP2SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP2SR3_3_0     FM(QSPI0_IO3)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_7_4     FM(QSPI0_IO2)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_11_8    FM(QSPI0_MISO_IO1)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_15_12   FM(QSPI0_MOSI_IO0)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_19_16   FM(QSPI0_SPCLK)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_23_20   FM(QSPI1_MOSI_IO0)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_27_24   FM(QSPI1_SPCLK)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_31_28   FM(QSPI1_MISO_IO1)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP3SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP3SR3_3_0     FM(QSPI1_IO2)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_7_4     FM(QSPI1_SSL)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_11_8    FM(QSPI1_IO3)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_15_12   FM(RPC_RESET_N)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_19_16   FM(RPC_WP_N)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_23_20   FM(RPC_INT_N)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR3 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR3_3_0     FM(MMC_SD_D1)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_7_4     FM(MMC_SD_D0)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_11_8    FM(MMC_SD_D2)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_15_12   FM(MMC_SD_CLK)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_19_16   FM(MMC_DS)              F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_23_20   FM(MMC_SD_D3)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_27_24   FM(MMC_D5)              F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_31_28   FM(MMC_D4)              F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR3 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR3_3_0     FM(MMC_D7)              F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_7_4     FM(MMC_D6)              F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_11_8    FM(MMC_SD_CMD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_15_12   FM(SD_CD)               F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_19_16   FM(SD_WP)               F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20   FM(IPC_CLKIN)           FM(IPC_CLKEN_IN)        FM(PWM1_A)              FM(TCLK3_X)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24   FM(IPC_CLKOUT)          FM(IPC_CLKEN_OUT)       FM(ERROROUTC_N_A)       FM(TCLK4_X)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_31_28   FM(QSPI0_SSL)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR3 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR3_3_0     FM(QSPI0_IO3)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_7_4     FM(QSPI0_IO2)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_11_8    FM(QSPI0_MISO_IO1)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_15_12   FM(QSPI0_MOSI_IO0)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_19_16   FM(QSPI0_SPCLK)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_23_20   FM(QSPI1_MOSI_IO0)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_27_24   FM(QSPI1_SPCLK)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_31_28   FM(QSPI1_MISO_IO1)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR3 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP3SR3_3_0     FM(QSPI1_IO2)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_7_4     FM(QSPI1_SSL)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_11_8    FM(QSPI1_IO3)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_15_12   FM(RPC_RESET_N)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_19_16   FM(RPC_WP_N)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_23_20   FM(RPC_INT_N)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR4 */
+/* IP0SR4 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR4_3_0     FM(TSN0_MDIO)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_7_4     FM(TSN0_MDC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_11_8    FM(TSN0_AVTP_PPS1)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_15_12   FM(TSN0_PHY_INT)        F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_19_16   FM(TSN0_LINK)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_23_20   FM(TSN0_AVTP_MATCH)     F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_27_24   FM(TSN0_AVTP_CAPTURE)   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_31_28   FM(TSN0_RX_CTL)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR4 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR4_3_0     FM(TSN0_AVTP_PPS0)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_7_4     FM(TSN0_TX_CTL)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_11_8    FM(TSN0_RD0)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_15_12   FM(TSN0_RXC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_19_16   FM(TSN0_TXC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_23_20   FM(TSN0_RD1)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_27_24   FM(TSN0_TD1)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_31_28   FM(TSN0_TD0)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR4 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR4_3_0     FM(TSN0_RD3)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_7_4     FM(TSN0_RD2)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_11_8    FM(TSN0_TD3)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_15_12   FM(TSN0_TD2)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_19_16   FM(TSN0_TXCREFCLK)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_23_20   FM(PCIE0_CLKREQ_N)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_27_24   FM(PCIE1_CLKREQ_N)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_31_28   FM(AVS0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR4 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP3SR4_3_0     FM(AVS1)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR5 */
+/* IP0SR5 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR5_3_0     FM(AVB2_AVTP_PPS)       F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_7_4     FM(AVB2_AVTP_CAPTURE)   F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_11_8    FM(AVB2_AVTP_MATCH)     F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_15_12   FM(AVB2_LINK)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_19_16   FM(AVB2_PHY_INT)        F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_23_20   FM(AVB2_MAGIC)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_27_24   FM(AVB2_MDC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_31_28   FM(AVB2_TXCREFCLK)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR5 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR5_3_0     FM(AVB2_TD3)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_7_4     FM(AVB2_RD3)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_11_8    FM(AVB2_MDIO)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_15_12   FM(AVB2_TD2)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_19_16   FM(AVB2_TD1)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_23_20   FM(AVB2_RD2)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_27_24   FM(AVB2_RD1)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_31_28   FM(AVB2_TD0)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR5 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR5_3_0     FM(AVB2_TXC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_7_4     FM(AVB2_RD0)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_11_8    FM(AVB2_RXC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_15_12   FM(AVB2_TX_CTL)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_19_16   FM(AVB2_RX_CTL)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR6 */
-/* IP0SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR6_3_0     FM(AVB1_MDIO)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_7_4     FM(AVB1_MAGIC)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_11_8    FM(AVB1_MDC)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_15_12   FM(AVB1_PHY_INT)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_19_16   FM(AVB1_LINK)           FM(AVB1_MII_TX_ER)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_23_20   FM(AVB1_AVTP_MATCH)     FM(AVB1_MII_RX_ER)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_27_24   FM(AVB1_TXC)            FM(AVB1_MII_TXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_31_28   FM(AVB1_TX_CTL)         FM(AVB1_MII_TX_EN)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR6_3_0     FM(AVB1_RXC)            FM(AVB1_MII_RXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_7_4     FM(AVB1_RX_CTL)         FM(AVB1_MII_RX_DV)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_11_8    FM(AVB1_AVTP_PPS)       FM(AVB1_MII_COL)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_15_12   FM(AVB1_AVTP_CAPTURE)   FM(AVB1_MII_CRS)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_19_16   FM(AVB1_TD1)            FM(AVB1_MII_TD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_23_20   FM(AVB1_TD0)            FM(AVB1_MII_TD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_27_24   FM(AVB1_RD1)            FM(AVB1_MII_RD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_31_28   FM(AVB1_RD0)            FM(AVB1_MII_RD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP2SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP2SR6_3_0     FM(AVB1_TD2)            FM(AVB1_MII_TD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_7_4     FM(AVB1_RD2)            FM(AVB1_MII_RD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_11_8    FM(AVB1_TD3)            FM(AVB1_MII_TD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_15_12   FM(AVB1_RD3)            FM(AVB1_MII_RD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_19_16   FM(AVB1_TXCREFCLK)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR6 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR6_3_0     FM(AVB1_MDIO)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_7_4     FM(AVB1_MAGIC)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_11_8    FM(AVB1_MDC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_15_12   FM(AVB1_PHY_INT)        F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_19_16   FM(AVB1_LINK)           FM(AVB1_MII_TX_ER)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_23_20   FM(AVB1_AVTP_MATCH)     FM(AVB1_MII_RX_ER)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_27_24   FM(AVB1_TXC)            FM(AVB1_MII_TXC)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_31_28   FM(AVB1_TX_CTL)         FM(AVB1_MII_TX_EN)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR6 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR6_3_0     FM(AVB1_RXC)            FM(AVB1_MII_RXC)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_7_4     FM(AVB1_RX_CTL)         FM(AVB1_MII_RX_DV)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_11_8    FM(AVB1_AVTP_PPS)       FM(AVB1_MII_COL)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_15_12   FM(AVB1_AVTP_CAPTURE)   FM(AVB1_MII_CRS)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_19_16   FM(AVB1_TD1)            FM(AVB1_MII_TD1)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_23_20   FM(AVB1_TD0)            FM(AVB1_MII_TD0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_27_24   FM(AVB1_RD1)            FM(AVB1_MII_RD1)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_31_28   FM(AVB1_RD0)            FM(AVB1_MII_RD0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR6 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR6_3_0     FM(AVB1_TD2)            FM(AVB1_MII_TD2)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_7_4     FM(AVB1_RD2)            FM(AVB1_MII_RD2)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_11_8    FM(AVB1_TD3)            FM(AVB1_MII_TD3)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_15_12   FM(AVB1_RD3)            FM(AVB1_MII_RD3)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_19_16   FM(AVB1_TXCREFCLK)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR7 */
-/* IP0SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR7_3_0     FM(AVB0_AVTP_PPS)       FM(AVB0_MII_COL)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_7_4     FM(AVB0_AVTP_CAPTURE)   FM(AVB0_MII_CRS)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_11_8    FM(AVB0_AVTP_MATCH)     FM(AVB0_MII_RX_ER)      FM(CC5_OSCOUT)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_15_12   FM(AVB0_TD3)            FM(AVB0_MII_TD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_19_16   FM(AVB0_LINK)           FM(AVB0_MII_TX_ER)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_23_20   FM(AVB0_PHY_INT)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_27_24   FM(AVB0_TD2)            FM(AVB0_MII_TD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_31_28   FM(AVB0_TD1)            FM(AVB0_MII_TD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR7_3_0     FM(AVB0_RD3)            FM(AVB0_MII_RD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_7_4     FM(AVB0_TXCREFCLK)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_11_8    FM(AVB0_MAGIC)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_15_12   FM(AVB0_TD0)            FM(AVB0_MII_TD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_19_16   FM(AVB0_RD2)            FM(AVB0_MII_RD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_23_20   FM(AVB0_MDC)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_27_24   FM(AVB0_MDIO)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_31_28   FM(AVB0_TXC)            FM(AVB0_MII_TXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP2SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP2SR7_3_0     FM(AVB0_TX_CTL)         FM(AVB0_MII_TX_EN)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_7_4     FM(AVB0_RD1)            FM(AVB0_MII_RD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_11_8    FM(AVB0_RD0)            FM(AVB0_MII_RD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_15_12   FM(AVB0_RXC)            FM(AVB0_MII_RXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_19_16   FM(AVB0_RX_CTL)         FM(AVB0_MII_RX_DV)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR7 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR7_3_0     FM(AVB0_AVTP_PPS)       FM(AVB0_MII_COL)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_7_4     FM(AVB0_AVTP_CAPTURE)   FM(AVB0_MII_CRS)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_11_8    FM(AVB0_AVTP_MATCH)     FM(AVB0_MII_RX_ER)      FM(CC5_OSCOUT)          F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_15_12   FM(AVB0_TD3)            FM(AVB0_MII_TD3)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_19_16   FM(AVB0_LINK)           FM(AVB0_MII_TX_ER)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_23_20   FM(AVB0_PHY_INT)        F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_27_24   FM(AVB0_TD2)            FM(AVB0_MII_TD2)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_31_28   FM(AVB0_TD1)            FM(AVB0_MII_TD1)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR7 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR7_3_0     FM(AVB0_RD3)            FM(AVB0_MII_RD3)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_7_4     FM(AVB0_TXCREFCLK)      F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_11_8    FM(AVB0_MAGIC)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_15_12   FM(AVB0_TD0)            FM(AVB0_MII_TD0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_19_16   FM(AVB0_RD2)            FM(AVB0_MII_RD2)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_23_20   FM(AVB0_MDC)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_27_24   FM(AVB0_MDIO)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_31_28   FM(AVB0_TXC)            FM(AVB0_MII_TXC)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR7 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR7_3_0     FM(AVB0_TX_CTL)         FM(AVB0_MII_TX_EN)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_7_4     FM(AVB0_RD1)            FM(AVB0_MII_RD1)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_11_8    FM(AVB0_RD0)            FM(AVB0_MII_RD0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_15_12   FM(AVB0_RXC)            FM(AVB0_MII_RXC)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_19_16   FM(AVB0_RX_CTL)         FM(AVB0_MII_RX_DV)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* SR8 */
-/* IP0SR8 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP0SR8_3_0     FM(SCL0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_7_4     FM(SDA0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_11_8    FM(SCL1)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_15_12   FM(SDA1)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_19_16   FM(SCL2)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_23_20   FM(SDA2)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_27_24   FM(SCL3)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_31_28   FM(SDA3)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IP1SR8 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR8_3_0     FM(SCL4)                FM(HRX2)                FM(SCK4)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_7_4     FM(SDA4)                FM(HTX2)                FM(CTS4_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_11_8    FM(SCL5)                FM(HRTS2_N)             FM(RTS4_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_15_12   FM(SDA5)                FM(SCIF_CLK2)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_19_16   F_(0, 0)                FM(HCTS2_N)             FM(TX4)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_23_20   F_(0, 0)                FM(HSCK2)               FM(RX4)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR8 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR8_3_0     FM(SCL0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_7_4     FM(SDA0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_11_8    FM(SCL1)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_15_12   FM(SDA1)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_19_16   FM(SCL2)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_23_20   FM(SDA2)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_27_24   FM(SCL3)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_31_28   FM(SDA3)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR8 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR8_3_0     FM(SCL4)                FM(HRX2)                FM(SCK4)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_7_4     FM(SDA4)                FM(HTX2)                FM(CTS4_N)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_11_8    FM(SCL5)                FM(HRTS2_N)             FM(RTS4_N)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_15_12   FM(SDA5)                FM(SCIF_CLK2)           F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_19_16   F_(0, 0)                FM(HCTS2_N)             FM(TX4)                 F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_23_20   F_(0, 0)                FM(HSCK2)               FM(RX4)                 F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 #define PINMUX_GPSR    \
                                                GPSR3_29                                                                                        \
@@ -545,6 +613,24 @@ FM(IP0SR3_23_20)   IP0SR3_23_20    FM(IP1SR3_23_20)        IP1SR3_23_20    FM(IP2SR3_23_20)        IP2
 FM(IP0SR3_27_24)       IP0SR3_27_24    FM(IP1SR3_27_24)        IP1SR3_27_24    FM(IP2SR3_27_24)        IP2SR3_27_24                                            \
 FM(IP0SR3_31_28)       IP0SR3_31_28    FM(IP1SR3_31_28)        IP1SR3_31_28    FM(IP2SR3_31_28)        IP2SR3_31_28                                            \
 \
+FM(IP0SR4_3_0)         IP0SR4_3_0      FM(IP1SR4_3_0)          IP1SR4_3_0      FM(IP2SR4_3_0)          IP2SR4_3_0      FM(IP3SR4_3_0)          IP3SR4_3_0      \
+FM(IP0SR4_7_4)         IP0SR4_7_4      FM(IP1SR4_7_4)          IP1SR4_7_4      FM(IP2SR4_7_4)          IP2SR4_7_4      \
+FM(IP0SR4_11_8)                IP0SR4_11_8     FM(IP1SR4_11_8)         IP1SR4_11_8     FM(IP2SR4_11_8)         IP2SR4_11_8     \
+FM(IP0SR4_15_12)       IP0SR4_15_12    FM(IP1SR4_15_12)        IP1SR4_15_12    FM(IP2SR4_15_12)        IP2SR4_15_12    \
+FM(IP0SR4_19_16)       IP0SR4_19_16    FM(IP1SR4_19_16)        IP1SR4_19_16    FM(IP2SR4_19_16)        IP2SR4_19_16    \
+FM(IP0SR4_23_20)       IP0SR4_23_20    FM(IP1SR4_23_20)        IP1SR4_23_20    FM(IP2SR4_23_20)        IP2SR4_23_20    \
+FM(IP0SR4_27_24)       IP0SR4_27_24    FM(IP1SR4_27_24)        IP1SR4_27_24    FM(IP2SR4_27_24)        IP2SR4_27_24    \
+FM(IP0SR4_31_28)       IP0SR4_31_28    FM(IP1SR4_31_28)        IP1SR4_31_28    FM(IP2SR4_31_28)        IP2SR4_31_28    \
+\
+FM(IP0SR5_3_0)         IP0SR5_3_0      FM(IP1SR5_3_0)          IP1SR5_3_0      FM(IP2SR5_3_0)          IP2SR5_3_0      \
+FM(IP0SR5_7_4)         IP0SR5_7_4      FM(IP1SR5_7_4)          IP1SR5_7_4      FM(IP2SR5_7_4)          IP2SR5_7_4      \
+FM(IP0SR5_11_8)                IP0SR5_11_8     FM(IP1SR5_11_8)         IP1SR5_11_8     FM(IP2SR5_11_8)         IP2SR5_11_8     \
+FM(IP0SR5_15_12)       IP0SR5_15_12    FM(IP1SR5_15_12)        IP1SR5_15_12    FM(IP2SR5_15_12)        IP2SR5_15_12    \
+FM(IP0SR5_19_16)       IP0SR5_19_16    FM(IP1SR5_19_16)        IP1SR5_19_16    FM(IP2SR5_19_16)        IP2SR5_19_16    \
+FM(IP0SR5_23_20)       IP0SR5_23_20    FM(IP1SR5_23_20)        IP1SR5_23_20    \
+FM(IP0SR5_27_24)       IP0SR5_27_24    FM(IP1SR5_27_24)        IP1SR5_27_24    \
+FM(IP0SR5_31_28)       IP0SR5_31_28    FM(IP1SR5_31_28)        IP1SR5_31_28    \
+\
 FM(IP0SR6_3_0)         IP0SR6_3_0      FM(IP1SR6_3_0)          IP1SR6_3_0      FM(IP2SR6_3_0)          IP2SR6_3_0      \
 FM(IP0SR6_7_4)         IP0SR6_7_4      FM(IP1SR6_7_4)          IP1SR6_7_4      FM(IP2SR6_7_4)          IP2SR6_7_4      \
 FM(IP0SR6_11_8)                IP0SR6_11_8     FM(IP1SR6_11_8)         IP1SR6_11_8     FM(IP2SR6_11_8)         IP2SR6_11_8     \
@@ -572,54 +658,6 @@ FM(IP0SR8_23_20)   IP0SR8_23_20    FM(IP1SR8_23_20)        IP1SR8_23_20    \
 FM(IP0SR8_27_24)       IP0SR8_27_24    \
 FM(IP0SR8_31_28)       IP0SR8_31_28
 
-/* MOD_SEL4 */                 /* 0 */                         /* 1 */
-#define MOD_SEL4_19            FM(SEL_TSN0_TD2_0)              FM(SEL_TSN0_TD2_1)
-#define MOD_SEL4_18            FM(SEL_TSN0_TD3_0)              FM(SEL_TSN0_TD3_1)
-#define MOD_SEL4_15            FM(SEL_TSN0_TD0_0)              FM(SEL_TSN0_TD0_1)
-#define MOD_SEL4_14            FM(SEL_TSN0_TD1_0)              FM(SEL_TSN0_TD1_1)
-#define MOD_SEL4_12            FM(SEL_TSN0_TXC_0)              FM(SEL_TSN0_TXC_1)
-#define MOD_SEL4_9             FM(SEL_TSN0_TX_CTL_0)           FM(SEL_TSN0_TX_CTL_1)
-#define MOD_SEL4_8             FM(SEL_TSN0_AVTP_PPS0_0)        FM(SEL_TSN0_AVTP_PPS0_1)
-#define MOD_SEL4_5             FM(SEL_TSN0_AVTP_MATCH_0)       FM(SEL_TSN0_AVTP_MATCH_1)
-#define MOD_SEL4_2             FM(SEL_TSN0_AVTP_PPS1_0)        FM(SEL_TSN0_AVTP_PPS1_1)
-#define MOD_SEL4_1             FM(SEL_TSN0_MDC_0)              FM(SEL_TSN0_MDC_1)
-
-/* MOD_SEL5 */                 /* 0 */                         /* 1 */
-#define MOD_SEL5_19            FM(SEL_AVB2_TX_CTL_0)           FM(SEL_AVB2_TX_CTL_1)
-#define MOD_SEL5_16            FM(SEL_AVB2_TXC_0)              FM(SEL_AVB2_TXC_1)
-#define MOD_SEL5_15            FM(SEL_AVB2_TD0_0)              FM(SEL_AVB2_TD0_1)
-#define MOD_SEL5_12            FM(SEL_AVB2_TD1_0)              FM(SEL_AVB2_TD1_1)
-#define MOD_SEL5_11            FM(SEL_AVB2_TD2_0)              FM(SEL_AVB2_TD2_1)
-#define MOD_SEL5_8             FM(SEL_AVB2_TD3_0)              FM(SEL_AVB2_TD3_1)
-#define MOD_SEL5_6             FM(SEL_AVB2_MDC_0)              FM(SEL_AVB2_MDC_1)
-#define MOD_SEL5_5             FM(SEL_AVB2_MAGIC_0)            FM(SEL_AVB2_MAGIC_1)
-#define MOD_SEL5_2             FM(SEL_AVB2_AVTP_MATCH_0)       FM(SEL_AVB2_AVTP_MATCH_1)
-#define MOD_SEL5_0             FM(SEL_AVB2_AVTP_PPS_0)         FM(SEL_AVB2_AVTP_PPS_1)
-
-/* MOD_SEL6 */                 /* 0 */                         /* 1 */
-#define MOD_SEL6_18            FM(SEL_AVB1_TD3_0)              FM(SEL_AVB1_TD3_1)
-#define MOD_SEL6_16            FM(SEL_AVB1_TD2_0)              FM(SEL_AVB1_TD2_1)
-#define MOD_SEL6_13            FM(SEL_AVB1_TD0_0)              FM(SEL_AVB1_TD0_1)
-#define MOD_SEL6_12            FM(SEL_AVB1_TD1_0)              FM(SEL_AVB1_TD1_1)
-#define MOD_SEL6_10            FM(SEL_AVB1_AVTP_PPS_0)         FM(SEL_AVB1_AVTP_PPS_1)
-#define MOD_SEL6_7             FM(SEL_AVB1_TX_CTL_0)           FM(SEL_AVB1_TX_CTL_1)
-#define MOD_SEL6_6             FM(SEL_AVB1_TXC_0)              FM(SEL_AVB1_TXC_1)
-#define MOD_SEL6_5             FM(SEL_AVB1_AVTP_MATCH_0)       FM(SEL_AVB1_AVTP_MATCH_1)
-#define MOD_SEL6_2             FM(SEL_AVB1_MDC_0)              FM(SEL_AVB1_MDC_1)
-#define MOD_SEL6_1             FM(SEL_AVB1_MAGIC_0)            FM(SEL_AVB1_MAGIC_1)
-
-/* MOD_SEL7 */                 /* 0 */                         /* 1 */
-#define MOD_SEL7_16            FM(SEL_AVB0_TX_CTL_0)           FM(SEL_AVB0_TX_CTL_1)
-#define MOD_SEL7_15            FM(SEL_AVB0_TXC_0)              FM(SEL_AVB0_TXC_1)
-#define MOD_SEL7_13            FM(SEL_AVB0_MDC_0)              FM(SEL_AVB0_MDC_1)
-#define MOD_SEL7_11            FM(SEL_AVB0_TD0_0)              FM(SEL_AVB0_TD0_1)
-#define MOD_SEL7_10            FM(SEL_AVB0_MAGIC_0)            FM(SEL_AVB0_MAGIC_1)
-#define MOD_SEL7_7             FM(SEL_AVB0_TD1_0)              FM(SEL_AVB0_TD1_1)
-#define MOD_SEL7_6             FM(SEL_AVB0_TD2_0)              FM(SEL_AVB0_TD2_1)
-#define MOD_SEL7_3             FM(SEL_AVB0_TD3_0)              FM(SEL_AVB0_TD3_1)
-#define MOD_SEL7_2             FM(SEL_AVB0_AVTP_MATCH_0)       FM(SEL_AVB0_AVTP_MATCH_1)
-#define MOD_SEL7_0             FM(SEL_AVB0_AVTP_PPS_0)         FM(SEL_AVB0_AVTP_PPS_1)
-
 /* MOD_SEL8 */                 /* 0 */                         /* 1 */
 #define MOD_SEL8_11            FM(SEL_SDA5_0)                  FM(SEL_SDA5_1)
 #define MOD_SEL8_10            FM(SEL_SCL5_0)                  FM(SEL_SCL5_1)
@@ -636,26 +674,18 @@ FM(IP0SR8_31_28)  IP0SR8_31_28
 
 #define PINMUX_MOD_SELS \
 \
-MOD_SEL4_19            MOD_SEL5_19                                                                             \
-MOD_SEL4_18                                    MOD_SEL6_18                                                     \
-                                                                                                               \
-                       MOD_SEL5_16             MOD_SEL6_16             MOD_SEL7_16                             \
-MOD_SEL4_15            MOD_SEL5_15                                     MOD_SEL7_15                             \
-MOD_SEL4_14                                                                                                    \
-                                               MOD_SEL6_13             MOD_SEL7_13                             \
-MOD_SEL4_12            MOD_SEL5_12             MOD_SEL6_12                                                     \
-                       MOD_SEL5_11                                     MOD_SEL7_11             MOD_SEL8_11     \
-                                               MOD_SEL6_10             MOD_SEL7_10             MOD_SEL8_10     \
-MOD_SEL4_9                                                                                     MOD_SEL8_9      \
-MOD_SEL4_8             MOD_SEL5_8                                                              MOD_SEL8_8      \
-                                               MOD_SEL6_7              MOD_SEL7_7              MOD_SEL8_7      \
-                       MOD_SEL5_6              MOD_SEL6_6              MOD_SEL7_6              MOD_SEL8_6      \
-MOD_SEL4_5             MOD_SEL5_5              MOD_SEL6_5                                      MOD_SEL8_5      \
-                                                                                               MOD_SEL8_4      \
-                                                                       MOD_SEL7_3              MOD_SEL8_3      \
-MOD_SEL4_2             MOD_SEL5_2              MOD_SEL6_2              MOD_SEL7_2              MOD_SEL8_2      \
-MOD_SEL4_1                                     MOD_SEL6_1                                      MOD_SEL8_1      \
-                       MOD_SEL5_0                                      MOD_SEL7_0              MOD_SEL8_0
+MOD_SEL8_11    \
+MOD_SEL8_10    \
+MOD_SEL8_9     \
+MOD_SEL8_8     \
+MOD_SEL8_7     \
+MOD_SEL8_6     \
+MOD_SEL8_5     \
+MOD_SEL8_4     \
+MOD_SEL8_3     \
+MOD_SEL8_2     \
+MOD_SEL8_1     \
+MOD_SEL8_0
 
 enum {
        PINMUX_RESERVED = 0,
@@ -689,61 +719,8 @@ enum {
 static const u16 pinmux_data[] = {
        PINMUX_DATA_GP_ALL(),
 
-       PINMUX_SINGLE(AVS1),
-       PINMUX_SINGLE(AVS0),
-       PINMUX_SINGLE(PCIE1_CLKREQ_N),
-       PINMUX_SINGLE(PCIE0_CLKREQ_N),
-
-       /* TSN0 without MODSEL4 */
-       PINMUX_SINGLE(TSN0_TXCREFCLK),
-       PINMUX_SINGLE(TSN0_RD2),
-       PINMUX_SINGLE(TSN0_RD3),
-       PINMUX_SINGLE(TSN0_RD1),
-       PINMUX_SINGLE(TSN0_RXC),
-       PINMUX_SINGLE(TSN0_RD0),
-       PINMUX_SINGLE(TSN0_RX_CTL),
-       PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
-       PINMUX_SINGLE(TSN0_LINK),
-       PINMUX_SINGLE(TSN0_PHY_INT),
-       PINMUX_SINGLE(TSN0_MDIO),
-       /* TSN0 with MODSEL4 */
-       PINMUX_IPSR_NOGM(0, TSN0_TD2,           SEL_TSN0_TD2_1),
-       PINMUX_IPSR_NOGM(0, TSN0_TD3,           SEL_TSN0_TD3_1),
-       PINMUX_IPSR_NOGM(0, TSN0_TD0,           SEL_TSN0_TD0_1),
-       PINMUX_IPSR_NOGM(0, TSN0_TD1,           SEL_TSN0_TD1_1),
-       PINMUX_IPSR_NOGM(0, TSN0_TXC,           SEL_TSN0_TXC_1),
-       PINMUX_IPSR_NOGM(0, TSN0_TX_CTL,        SEL_TSN0_TX_CTL_1),
-       PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0,     SEL_TSN0_AVTP_PPS0_1),
-       PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH,    SEL_TSN0_AVTP_MATCH_1),
-       PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1,     SEL_TSN0_AVTP_PPS1_1),
-       PINMUX_IPSR_NOGM(0, TSN0_MDC,           SEL_TSN0_MDC_1),
-
-       /* TSN0 without MODSEL5 */
-       PINMUX_SINGLE(AVB2_RX_CTL),
-       PINMUX_SINGLE(AVB2_RXC),
-       PINMUX_SINGLE(AVB2_RD0),
-       PINMUX_SINGLE(AVB2_RD1),
-       PINMUX_SINGLE(AVB2_RD2),
-       PINMUX_SINGLE(AVB2_MDIO),
-       PINMUX_SINGLE(AVB2_RD3),
-       PINMUX_SINGLE(AVB2_TXCREFCLK),
-       PINMUX_SINGLE(AVB2_PHY_INT),
-       PINMUX_SINGLE(AVB2_LINK),
-       PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
-       /* TSN0 with MODSEL5 */
-       PINMUX_IPSR_NOGM(0, AVB2_TX_CTL,        SEL_AVB2_TX_CTL_1),
-       PINMUX_IPSR_NOGM(0, AVB2_TXC,           SEL_AVB2_TXC_1),
-       PINMUX_IPSR_NOGM(0, AVB2_TD0,           SEL_AVB2_TD0_1),
-       PINMUX_IPSR_NOGM(0, AVB2_TD1,           SEL_AVB2_TD1_1),
-       PINMUX_IPSR_NOGM(0, AVB2_TD2,           SEL_AVB2_TD2_1),
-       PINMUX_IPSR_NOGM(0, AVB2_TD3,           SEL_AVB2_TD3_1),
-       PINMUX_IPSR_NOGM(0, AVB2_MDC,           SEL_AVB2_MDC_1),
-       PINMUX_IPSR_NOGM(0, AVB2_MAGIC,         SEL_AVB2_MAGIC_1),
-       PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH,    SEL_AVB2_AVTP_MATCH_1),
-       PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS,      SEL_AVB2_AVTP_PPS_1),
-
        /* IP0SR0 */
-       PINMUX_IPSR_GPSR(IP0SR0_3_0,    ERROROUTC_B),
+       PINMUX_IPSR_GPSR(IP0SR0_3_0,    ERROROUTC_N_B),
        PINMUX_IPSR_GPSR(IP0SR0_3_0,    TCLK2_A),
 
        PINMUX_IPSR_GPSR(IP0SR0_7_4,    MSIOF3_SS1),
@@ -1009,7 +986,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP1SR3_27_24,  IPC_CLKOUT),
        PINMUX_IPSR_GPSR(IP1SR3_27_24,  IPC_CLKEN_OUT),
-       PINMUX_IPSR_GPSR(IP1SR3_27_24,  ERROROUTC_A),
+       PINMUX_IPSR_GPSR(IP1SR3_27_24,  ERROROUTC_N_A),
        PINMUX_IPSR_GPSR(IP1SR3_27_24,  TCLK4_X),
 
        PINMUX_IPSR_GPSR(IP1SR3_31_28,  QSPI0_SSL),
@@ -1032,26 +1009,86 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP3SR3_19_16,  RPC_WP_N),
        PINMUX_IPSR_GPSR(IP3SR3_23_20,  RPC_INT_N),
 
+       /* IP0SR4 */
+       PINMUX_IPSR_GPSR(IP0SR4_3_0,    TSN0_MDIO),
+       PINMUX_IPSR_GPSR(IP0SR4_7_4,    TSN0_MDC),
+       PINMUX_IPSR_GPSR(IP0SR4_11_8,   TSN0_AVTP_PPS1),
+       PINMUX_IPSR_GPSR(IP0SR4_15_12,  TSN0_PHY_INT),
+       PINMUX_IPSR_GPSR(IP0SR4_19_16,  TSN0_LINK),
+       PINMUX_IPSR_GPSR(IP0SR4_23_20,  TSN0_AVTP_MATCH),
+       PINMUX_IPSR_GPSR(IP0SR4_27_24,  TSN0_AVTP_CAPTURE),
+       PINMUX_IPSR_GPSR(IP0SR4_31_28,  TSN0_RX_CTL),
+
+       /* IP1SR4 */
+       PINMUX_IPSR_GPSR(IP1SR4_3_0,    TSN0_AVTP_PPS0),
+       PINMUX_IPSR_GPSR(IP1SR4_7_4,    TSN0_TX_CTL),
+       PINMUX_IPSR_GPSR(IP1SR4_11_8,   TSN0_RD0),
+       PINMUX_IPSR_GPSR(IP1SR4_15_12,  TSN0_RXC),
+       PINMUX_IPSR_GPSR(IP1SR4_19_16,  TSN0_TXC),
+       PINMUX_IPSR_GPSR(IP1SR4_23_20,  TSN0_RD1),
+       PINMUX_IPSR_GPSR(IP1SR4_27_24,  TSN0_TD1),
+       PINMUX_IPSR_GPSR(IP1SR4_31_28,  TSN0_TD0),
+
+       /* IP2SR4 */
+       PINMUX_IPSR_GPSR(IP2SR4_3_0,    TSN0_RD3),
+       PINMUX_IPSR_GPSR(IP2SR4_7_4,    TSN0_RD2),
+       PINMUX_IPSR_GPSR(IP2SR4_11_8,   TSN0_TD3),
+       PINMUX_IPSR_GPSR(IP2SR4_15_12,  TSN0_TD2),
+       PINMUX_IPSR_GPSR(IP2SR4_19_16,  TSN0_TXCREFCLK),
+       PINMUX_IPSR_GPSR(IP2SR4_23_20,  PCIE0_CLKREQ_N),
+       PINMUX_IPSR_GPSR(IP2SR4_27_24,  PCIE1_CLKREQ_N),
+       PINMUX_IPSR_GPSR(IP2SR4_31_28,  AVS0),
+
+       /* IP3SR4 */
+       PINMUX_IPSR_GPSR(IP3SR4_3_0,    AVS1),
+
+       /* IP0SR5 */
+       PINMUX_IPSR_GPSR(IP0SR5_3_0,    AVB2_AVTP_PPS),
+       PINMUX_IPSR_GPSR(IP0SR5_7_4,    AVB2_AVTP_CAPTURE),
+       PINMUX_IPSR_GPSR(IP0SR5_11_8,   AVB2_AVTP_MATCH),
+       PINMUX_IPSR_GPSR(IP0SR5_15_12,  AVB2_LINK),
+       PINMUX_IPSR_GPSR(IP0SR5_19_16,  AVB2_PHY_INT),
+       PINMUX_IPSR_GPSR(IP0SR5_23_20,  AVB2_MAGIC),
+       PINMUX_IPSR_GPSR(IP0SR5_27_24,  AVB2_MDC),
+       PINMUX_IPSR_GPSR(IP0SR5_31_28,  AVB2_TXCREFCLK),
+
+       /* IP1SR5 */
+       PINMUX_IPSR_GPSR(IP1SR5_3_0,    AVB2_TD3),
+       PINMUX_IPSR_GPSR(IP1SR5_7_4,    AVB2_RD3),
+       PINMUX_IPSR_GPSR(IP1SR5_11_8,   AVB2_MDIO),
+       PINMUX_IPSR_GPSR(IP1SR5_15_12,  AVB2_TD2),
+       PINMUX_IPSR_GPSR(IP1SR5_19_16,  AVB2_TD1),
+       PINMUX_IPSR_GPSR(IP1SR5_23_20,  AVB2_RD2),
+       PINMUX_IPSR_GPSR(IP1SR5_27_24,  AVB2_RD1),
+       PINMUX_IPSR_GPSR(IP1SR5_31_28,  AVB2_TD0),
+
+       /* IP2SR5 */
+       PINMUX_IPSR_GPSR(IP2SR5_3_0,    AVB2_TXC),
+       PINMUX_IPSR_GPSR(IP2SR5_7_4,    AVB2_RD0),
+       PINMUX_IPSR_GPSR(IP2SR5_11_8,   AVB2_RXC),
+       PINMUX_IPSR_GPSR(IP2SR5_15_12,  AVB2_TX_CTL),
+       PINMUX_IPSR_GPSR(IP2SR5_19_16,  AVB2_RX_CTL),
+
        /* IP0SR6 */
        PINMUX_IPSR_GPSR(IP0SR6_3_0,    AVB1_MDIO),
 
-       PINMUX_IPSR_MSEL(IP0SR6_7_4,    AVB1_MAGIC,             SEL_AVB1_MAGIC_1),
+       PINMUX_IPSR_GPSR(IP0SR6_7_4,    AVB1_MAGIC),
 
-       PINMUX_IPSR_MSEL(IP0SR6_11_8,   AVB1_MDC,               SEL_AVB1_MDC_1),
+       PINMUX_IPSR_GPSR(IP0SR6_11_8,   AVB1_MDC),
 
        PINMUX_IPSR_GPSR(IP0SR6_15_12,  AVB1_PHY_INT),
 
        PINMUX_IPSR_GPSR(IP0SR6_19_16,  AVB1_LINK),
        PINMUX_IPSR_GPSR(IP0SR6_19_16,  AVB1_MII_TX_ER),
 
-       PINMUX_IPSR_MSEL(IP0SR6_23_20,  AVB1_AVTP_MATCH,        SEL_AVB1_AVTP_MATCH_1),
-       PINMUX_IPSR_MSEL(IP0SR6_23_20,  AVB1_MII_RX_ER,         SEL_AVB1_AVTP_MATCH_0),
+       PINMUX_IPSR_GPSR(IP0SR6_23_20,  AVB1_AVTP_MATCH),
+       PINMUX_IPSR_GPSR(IP0SR6_23_20,  AVB1_MII_RX_ER),
 
-       PINMUX_IPSR_MSEL(IP0SR6_27_24,  AVB1_TXC,               SEL_AVB1_TXC_1),
-       PINMUX_IPSR_MSEL(IP0SR6_27_24,  AVB1_MII_TXC,           SEL_AVB1_TXC_0),
+       PINMUX_IPSR_GPSR(IP0SR6_27_24,  AVB1_TXC),
+       PINMUX_IPSR_GPSR(IP0SR6_27_24,  AVB1_MII_TXC),
 
-       PINMUX_IPSR_MSEL(IP0SR6_31_28,  AVB1_TX_CTL,            SEL_AVB1_TX_CTL_1),
-       PINMUX_IPSR_MSEL(IP0SR6_31_28,  AVB1_MII_TX_EN,         SEL_AVB1_TX_CTL_0),
+       PINMUX_IPSR_GPSR(IP0SR6_31_28,  AVB1_TX_CTL),
+       PINMUX_IPSR_GPSR(IP0SR6_31_28,  AVB1_MII_TX_EN),
 
        /* IP1SR6 */
        PINMUX_IPSR_GPSR(IP1SR6_3_0,    AVB1_RXC),
@@ -1060,17 +1097,17 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP1SR6_7_4,    AVB1_RX_CTL),
        PINMUX_IPSR_GPSR(IP1SR6_7_4,    AVB1_MII_RX_DV),
 
-       PINMUX_IPSR_MSEL(IP1SR6_11_8,   AVB1_AVTP_PPS,          SEL_AVB1_AVTP_PPS_1),
-       PINMUX_IPSR_MSEL(IP1SR6_11_8,   AVB1_MII_COL,           SEL_AVB1_AVTP_PPS_0),
+       PINMUX_IPSR_GPSR(IP1SR6_11_8,   AVB1_AVTP_PPS),
+       PINMUX_IPSR_GPSR(IP1SR6_11_8,   AVB1_MII_COL),
 
        PINMUX_IPSR_GPSR(IP1SR6_15_12,  AVB1_AVTP_CAPTURE),
        PINMUX_IPSR_GPSR(IP1SR6_15_12,  AVB1_MII_CRS),
 
-       PINMUX_IPSR_MSEL(IP1SR6_19_16,  AVB1_TD1,               SEL_AVB1_TD1_1),
-       PINMUX_IPSR_MSEL(IP1SR6_19_16,  AVB1_MII_TD1,           SEL_AVB1_TD1_0),
+       PINMUX_IPSR_GPSR(IP1SR6_19_16,  AVB1_TD1),
+       PINMUX_IPSR_GPSR(IP1SR6_19_16,  AVB1_MII_TD1),
 
-       PINMUX_IPSR_MSEL(IP1SR6_23_20,  AVB1_TD0,               SEL_AVB1_TD0_1),
-       PINMUX_IPSR_MSEL(IP1SR6_23_20,  AVB1_MII_TD0,           SEL_AVB1_TD0_0),
+       PINMUX_IPSR_GPSR(IP1SR6_23_20,  AVB1_TD0),
+       PINMUX_IPSR_GPSR(IP1SR6_23_20,  AVB1_MII_TD0),
 
        PINMUX_IPSR_GPSR(IP1SR6_27_24,  AVB1_RD1),
        PINMUX_IPSR_GPSR(IP1SR6_27_24,  AVB1_MII_RD1),
@@ -1079,14 +1116,14 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP1SR6_31_28,  AVB1_MII_RD0),
 
        /* IP2SR6 */
-       PINMUX_IPSR_MSEL(IP2SR6_3_0,    AVB1_TD2,               SEL_AVB1_TD2_1),
-       PINMUX_IPSR_MSEL(IP2SR6_3_0,    AVB1_MII_TD2,           SEL_AVB1_TD2_0),
+       PINMUX_IPSR_GPSR(IP2SR6_3_0,    AVB1_TD2),
+       PINMUX_IPSR_GPSR(IP2SR6_3_0,    AVB1_MII_TD2),
 
        PINMUX_IPSR_GPSR(IP2SR6_7_4,    AVB1_RD2),
        PINMUX_IPSR_GPSR(IP2SR6_7_4,    AVB1_MII_RD2),
 
-       PINMUX_IPSR_MSEL(IP2SR6_11_8,   AVB1_TD3,               SEL_AVB1_TD3_1),
-       PINMUX_IPSR_MSEL(IP2SR6_11_8,   AVB1_MII_TD3,           SEL_AVB1_TD3_0),
+       PINMUX_IPSR_GPSR(IP2SR6_11_8,   AVB1_TD3),
+       PINMUX_IPSR_GPSR(IP2SR6_11_8,   AVB1_MII_TD3),
 
        PINMUX_IPSR_GPSR(IP2SR6_15_12,  AVB1_RD3),
        PINMUX_IPSR_GPSR(IP2SR6_15_12,  AVB1_MII_RD3),
@@ -1094,29 +1131,29 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP2SR6_19_16,  AVB1_TXCREFCLK),
 
        /* IP0SR7 */
-       PINMUX_IPSR_MSEL(IP0SR7_3_0,    AVB0_AVTP_PPS,          SEL_AVB0_AVTP_PPS_1),
-       PINMUX_IPSR_MSEL(IP0SR7_3_0,    AVB0_MII_COL,           SEL_AVB0_AVTP_PPS_0),
+       PINMUX_IPSR_GPSR(IP0SR7_3_0,    AVB0_AVTP_PPS),
+       PINMUX_IPSR_GPSR(IP0SR7_3_0,    AVB0_MII_COL),
 
        PINMUX_IPSR_GPSR(IP0SR7_7_4,    AVB0_AVTP_CAPTURE),
        PINMUX_IPSR_GPSR(IP0SR7_7_4,    AVB0_MII_CRS),
 
-       PINMUX_IPSR_MSEL(IP0SR7_11_8,   AVB0_AVTP_MATCH,        SEL_AVB0_AVTP_MATCH_1),
-       PINMUX_IPSR_MSEL(IP0SR7_11_8,   AVB0_MII_RX_ER,         SEL_AVB0_AVTP_MATCH_0),
-       PINMUX_IPSR_MSEL(IP0SR7_11_8,   CC5_OSCOUT,             SEL_AVB0_AVTP_MATCH_0),
+       PINMUX_IPSR_GPSR(IP0SR7_11_8,   AVB0_AVTP_MATCH),
+       PINMUX_IPSR_GPSR(IP0SR7_11_8,   AVB0_MII_RX_ER),
+       PINMUX_IPSR_GPSR(IP0SR7_11_8,   CC5_OSCOUT),
 
-       PINMUX_IPSR_MSEL(IP0SR7_15_12,  AVB0_TD3,               SEL_AVB0_TD3_1),
-       PINMUX_IPSR_MSEL(IP0SR7_15_12,  AVB0_MII_TD3,           SEL_AVB0_TD3_0),
+       PINMUX_IPSR_GPSR(IP0SR7_15_12,  AVB0_TD3),
+       PINMUX_IPSR_GPSR(IP0SR7_15_12,  AVB0_MII_TD3),
 
        PINMUX_IPSR_GPSR(IP0SR7_19_16,  AVB0_LINK),
        PINMUX_IPSR_GPSR(IP0SR7_19_16,  AVB0_MII_TX_ER),
 
        PINMUX_IPSR_GPSR(IP0SR7_23_20,  AVB0_PHY_INT),
 
-       PINMUX_IPSR_MSEL(IP0SR7_27_24,  AVB0_TD2,               SEL_AVB0_TD2_1),
-       PINMUX_IPSR_MSEL(IP0SR7_27_24,  AVB0_MII_TD2,           SEL_AVB0_TD2_0),
+       PINMUX_IPSR_GPSR(IP0SR7_27_24,  AVB0_TD2),
+       PINMUX_IPSR_GPSR(IP0SR7_27_24,  AVB0_MII_TD2),
 
-       PINMUX_IPSR_MSEL(IP0SR7_31_28,  AVB0_TD1,               SEL_AVB0_TD1_1),
-       PINMUX_IPSR_MSEL(IP0SR7_31_28,  AVB0_MII_TD1,           SEL_AVB0_TD1_0),
+       PINMUX_IPSR_GPSR(IP0SR7_31_28,  AVB0_TD1),
+       PINMUX_IPSR_GPSR(IP0SR7_31_28,  AVB0_MII_TD1),
 
        /* IP1SR7 */
        PINMUX_IPSR_GPSR(IP1SR7_3_0,    AVB0_RD3),
@@ -1124,24 +1161,24 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP1SR7_7_4,    AVB0_TXCREFCLK),
 
-       PINMUX_IPSR_MSEL(IP1SR7_11_8,   AVB0_MAGIC,             SEL_AVB0_MAGIC_1),
+       PINMUX_IPSR_GPSR(IP1SR7_11_8,   AVB0_MAGIC),
 
-       PINMUX_IPSR_MSEL(IP1SR7_15_12,  AVB0_TD0,               SEL_AVB0_TD0_1),
-       PINMUX_IPSR_MSEL(IP1SR7_15_12,  AVB0_MII_TD0,           SEL_AVB0_TD0_0),
+       PINMUX_IPSR_GPSR(IP1SR7_15_12,  AVB0_TD0),
+       PINMUX_IPSR_GPSR(IP1SR7_15_12,  AVB0_MII_TD0),
 
        PINMUX_IPSR_GPSR(IP1SR7_19_16,  AVB0_RD2),
        PINMUX_IPSR_GPSR(IP1SR7_19_16,  AVB0_MII_RD2),
 
-       PINMUX_IPSR_MSEL(IP1SR7_23_20,  AVB0_MDC,               SEL_AVB0_MDC_1),
+       PINMUX_IPSR_GPSR(IP1SR7_23_20,  AVB0_MDC),
 
        PINMUX_IPSR_GPSR(IP1SR7_27_24,  AVB0_MDIO),
 
-       PINMUX_IPSR_MSEL(IP1SR7_31_28,  AVB0_TXC,               SEL_AVB0_TXC_1),
-       PINMUX_IPSR_MSEL(IP1SR7_31_28,  AVB0_MII_TXC,           SEL_AVB0_TXC_0),
+       PINMUX_IPSR_GPSR(IP1SR7_31_28,  AVB0_TXC),
+       PINMUX_IPSR_GPSR(IP1SR7_31_28,  AVB0_MII_TXC),
 
        /* IP2SR7 */
-       PINMUX_IPSR_MSEL(IP2SR7_3_0,    AVB0_TX_CTL,            SEL_AVB0_TX_CTL_1),
-       PINMUX_IPSR_MSEL(IP2SR7_3_0,    AVB0_MII_TX_EN,         SEL_AVB0_TX_CTL_0),
+       PINMUX_IPSR_GPSR(IP2SR7_3_0,    AVB0_TX_CTL),
+       PINMUX_IPSR_GPSR(IP2SR7_3_0,    AVB0_MII_TX_EN),
 
        PINMUX_IPSR_GPSR(IP2SR7_7_4,    AVB0_RD1),
        PINMUX_IPSR_GPSR(IP2SR7_7_4,    AVB0_MII_RD1),
@@ -1193,10 +1230,28 @@ static const u16 pinmux_data[] = {
  */
 enum {
        GP_ASSIGN_LAST(),
+       NOGP_ALL(),
 };
 
 static const struct sh_pfc_pin pinmux_pins[] = {
        PINMUX_GPIO_GP_ALL(),
+       PINMUX_NOGP_ALL(),
+};
+
+/* - AUDIO CLOCK ----------------------------------------- */
+static const unsigned int audio_clkin_pins[] = {
+       /* CLK IN */
+       RCAR_GP_PIN(1, 22),
+};
+static const unsigned int audio_clkin_mux[] = {
+       AUDIO_CLKIN_MARK,
+};
+static const unsigned int audio_clkout_pins[] = {
+       /* CLK OUT */
+       RCAR_GP_PIN(1, 21),
+};
+static const unsigned int audio_clkout_mux[] = {
+       AUDIO_CLKOUT_MARK,
 };
 
 /* - AVB0 ------------------------------------------------ */
@@ -2332,6 +2387,22 @@ static const unsigned int scif_clk_mux[] = {
        SCIF_CLK_MARK,
 };
 
+/* - SSI ------------------------------------------------- */
+static const unsigned int ssi_data_pins[] = {
+       /* SSI_SD */
+       RCAR_GP_PIN(1, 20),
+};
+static const unsigned int ssi_data_mux[] = {
+       SSI_SD_MARK,
+};
+static const unsigned int ssi_ctrl_pins[] = {
+       /* SSI_SCK,  SSI_WS */
+       RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+};
+static const unsigned int ssi_ctrl_mux[] = {
+       SSI_SCK_MARK, SSI_WS_MARK,
+};
+
 /* - TPU ------------------------------------------------------------------- */
 static const unsigned int tpu_to0_pins[] = {
        /* TPU0TO0 */
@@ -2464,6 +2535,9 @@ static const unsigned int tsn0_avtp_match_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+       SH_PFC_PIN_GROUP(audio_clkin),
+       SH_PFC_PIN_GROUP(audio_clkout),
+
        SH_PFC_PIN_GROUP(avb0_link),
        SH_PFC_PIN_GROUP(avb0_magic),
        SH_PFC_PIN_GROUP(avb0_phy_int),
@@ -2624,6 +2698,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(scif4_ctrl),
        SH_PFC_PIN_GROUP(scif_clk),
 
+       SH_PFC_PIN_GROUP(ssi_data),
+       SH_PFC_PIN_GROUP(ssi_ctrl),
+
        SH_PFC_PIN_GROUP(tpu_to0),              /* suffix might be updated */
        SH_PFC_PIN_GROUP(tpu_to0_a),            /* suffix might be updated */
        SH_PFC_PIN_GROUP(tpu_to1),              /* suffix might be updated */
@@ -2643,6 +2720,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(tsn0_avtp_match),
 };
 
+static const char * const audio_clk_groups[] = {
+       "audio_clkin",
+       "audio_clkout",
+};
+
 static const char * const avb0_groups[] = {
        "avb0_link",
        "avb0_magic",
@@ -2936,6 +3018,11 @@ static const char * const scif_clk_groups[] = {
        "scif_clk",
 };
 
+static const char * const ssi_groups[] = {
+       "ssi_data",
+       "ssi_ctrl",
+};
+
 static const char * const tpu_groups[] = {
        /* suffix might be updated */
        "tpu_to0",
@@ -2960,6 +3047,8 @@ static const char * const tsn0_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+       SH_PFC_FUNCTION(audio_clk),
+
        SH_PFC_FUNCTION(avb0),
        SH_PFC_FUNCTION(avb1),
        SH_PFC_FUNCTION(avb2),
@@ -3017,6 +3106,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(scif4),
        SH_PFC_FUNCTION(scif_clk),
 
+       SH_PFC_FUNCTION(ssi),
+
        SH_PFC_FUNCTION(tpu),
 
        SH_PFC_FUNCTION(tsn0),
@@ -3422,6 +3513,82 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP3SR3_7_4
                IP3SR3_3_0))
        },
+       { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
+                            GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               IP0SR4_31_28
+               IP0SR4_27_24
+               IP0SR4_23_20
+               IP0SR4_19_16
+               IP0SR4_15_12
+               IP0SR4_11_8
+               IP0SR4_7_4
+               IP0SR4_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
+                            GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               IP1SR4_31_28
+               IP1SR4_27_24
+               IP1SR4_23_20
+               IP1SR4_19_16
+               IP1SR4_15_12
+               IP1SR4_11_8
+               IP1SR4_7_4
+               IP1SR4_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
+                            GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               IP2SR4_31_28
+               IP2SR4_27_24
+               IP2SR4_23_20
+               IP2SR4_19_16
+               IP2SR4_15_12
+               IP2SR4_11_8
+               IP2SR4_7_4
+               IP2SR4_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
+                            GROUP(-28, 4),
+                            GROUP(
+               /* IP3SR4_31_4 RESERVED */
+               IP3SR4_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
+                            GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               IP0SR5_31_28
+               IP0SR5_27_24
+               IP0SR5_23_20
+               IP0SR5_19_16
+               IP0SR5_15_12
+               IP0SR5_11_8
+               IP0SR5_7_4
+               IP0SR5_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
+                            GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               IP1SR5_31_28
+               IP1SR5_27_24
+               IP1SR5_23_20
+               IP1SR5_19_16
+               IP1SR5_15_12
+               IP1SR5_11_8
+               IP1SR5_7_4
+               IP1SR5_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
+                            GROUP(-12, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP2SR5_31_20 RESERVED */
+               IP2SR5_19_16
+               IP2SR5_15_12
+               IP2SR5_11_8
+               IP2SR5_7_4
+               IP2SR5_3_0))
+       },
        { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
                IP0SR6_31_28
                IP0SR6_27_24
@@ -3508,95 +3675,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 
 #define F_(x, y)       x,
 #define FM(x)          FN_##x,
-       { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
-                            GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1,
-                                  -2, 1, 1, -1),
-                            GROUP(
-               /* RESERVED 31-20 */
-               MOD_SEL4_19
-               MOD_SEL4_18
-               /* RESERVED 17-16 */
-               MOD_SEL4_15
-               MOD_SEL4_14
-               /* RESERVED 13 */
-               MOD_SEL4_12
-               /* RESERVED 11-10 */
-               MOD_SEL4_9
-               MOD_SEL4_8
-               /* RESERVED 7-6 */
-               MOD_SEL4_5
-               /* RESERVED 4-3 */
-               MOD_SEL4_2
-               MOD_SEL4_1
-               /* RESERVED 0 */
-               ))
-       },
-       { PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32,
-                            GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1,
-                                  1, 1, -2, 1, -1, 1),
-                            GROUP(
-               /* RESERVED 31-20 */
-               MOD_SEL5_19
-               /* RESERVED 18-17 */
-               MOD_SEL5_16
-               MOD_SEL5_15
-               /* RESERVED 14-13 */
-               MOD_SEL5_12
-               MOD_SEL5_11
-               /* RESERVED 10-9 */
-               MOD_SEL5_8
-               /* RESERVED 7 */
-               MOD_SEL5_6
-               MOD_SEL5_5
-               /* RESERVED 4-3 */
-               MOD_SEL5_2
-               /* RESERVED 1 */
-               MOD_SEL5_0))
-       },
-       { PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
-                            GROUP(-13, 1, -1, 1, -2, 1, 1,
-                                  -1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
-                            GROUP(
-               /* RESERVED 31-19 */
-               MOD_SEL6_18
-               /* RESERVED 17 */
-               MOD_SEL6_16
-               /* RESERVED 15-14 */
-               MOD_SEL6_13
-               MOD_SEL6_12
-               /* RESERVED 11 */
-               MOD_SEL6_10
-               /* RESERVED 9-8 */
-               MOD_SEL6_7
-               MOD_SEL6_6
-               MOD_SEL6_5
-               /* RESERVED 4-3 */
-               MOD_SEL6_2
-               MOD_SEL6_1
-               /* RESERVED 0 */
-               ))
-       },
-       { PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
-                            GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
-                                  -2, 1, 1, -1, 1),
-                            GROUP(
-               /* RESERVED 31-17 */
-               MOD_SEL7_16
-               MOD_SEL7_15
-               /* RESERVED 14 */
-               MOD_SEL7_13
-               /* RESERVED 12 */
-               MOD_SEL7_11
-               MOD_SEL7_10
-               /* RESERVED 9-8 */
-               MOD_SEL7_7
-               MOD_SEL7_6
-               /* RESERVED 5-4 */
-               MOD_SEL7_3
-               MOD_SEL7_2
-               /* RESERVED 1 */
-               MOD_SEL7_0))
-       },
        { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
                             GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
                             GROUP(
@@ -3614,7 +3692,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL8_1
                MOD_SEL8_0))
        },
-       { },
+       { /* sentinel */ }
 };
 
 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -3876,7 +3954,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
                { RCAR_GP_PIN(8,  9),  4, 3 },  /* SDA4 */
                { RCAR_GP_PIN(8,  8),  0, 3 },  /* SCL4 */
        } },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -3899,30 +3977,49 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POC6]          = { 0xE60610A0, },
        [POC7]          = { 0xE60618A0, },
        [POC8]          = { 0xE60680A0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
        int bit = pin & 0x1f;
 
-       *pocctrl = pinmux_ioctrl_regs[POC0].reg;
-       if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
+       switch (pin) {
+       case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
+               *pocctrl = pinmux_ioctrl_regs[POC0].reg;
                return bit;
 
-       *pocctrl = pinmux_ioctrl_regs[POC1].reg;
-       if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
+       case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
+               *pocctrl = pinmux_ioctrl_regs[POC1].reg;
                return bit;
 
-       *pocctrl = pinmux_ioctrl_regs[POC3].reg;
-       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
+       case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
+               *pocctrl = pinmux_ioctrl_regs[POC3].reg;
                return bit;
 
-       *pocctrl = pinmux_ioctrl_regs[POC8].reg;
-       if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
+       case PIN_VDDQ_TSN0:
+               *pocctrl = pinmux_ioctrl_regs[POC4].reg;
+               return 0;
+
+       case PIN_VDDQ_AVB2:
+               *pocctrl = pinmux_ioctrl_regs[POC5].reg;
+               return 0;
+
+       case PIN_VDDQ_AVB1:
+               *pocctrl = pinmux_ioctrl_regs[POC6].reg;
+               return 0;
+
+       case PIN_VDDQ_AVB0:
+               *pocctrl = pinmux_ioctrl_regs[POC7].reg;
+               return 0;
+
+       case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
+               *pocctrl = pinmux_ioctrl_regs[POC8].reg;
                return bit;
 
-       return -EINVAL;
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -4232,7 +4329,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [30] = SH_PFC_PIN_NONE,
                [31] = SH_PFC_PIN_NONE,
        } },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {

diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index f6e8dd93374ed6fd7ce57527969a04089303b2ed..3ac25cbd0806677f899e9399c6b6628dbb55bc1a 100644 (file)
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -798,7 +798,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
                return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 
        case PIN_CONFIG_POWER_SOURCE:
-               return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
+               return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
 
        default:
                return false;
@@ -814,6 +814,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
        int bit, ret;
        int idx = sh_pfc_get_pin_index(pfc, _pin);
        const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+       unsigned int mode, hi, lo;
 
        if (!sh_pfc_pinconf_validate(pfc, _pin, param))
                return -ENOTSUPP;
@@ -851,8 +852,12 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 
                pocctrl = (void __iomem *)(uintptr_t)addr;
 
+               mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
+               lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
+               hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
+
                val = sh_pfc_read_raw_reg(pocctrl, 32);
-               if (arg == ((pin->configs & SH_PFC_PIN_VOLTAGE_18_25) ? 2500 : 3300))
+               if (arg == hi)
                        val |= BIT(bit);
                else
                        val &= ~BIT(bit);

diff --git a/drivers/pinctrl/renesas/pfc-r7s72100.c b/drivers/pinctrl/renesas/pinctrl-rza1.c
similarity index 100%
rename from drivers/pinctrl/renesas/pfc-r7s72100.c
rename to drivers/pinctrl/renesas/pinctrl-rza1.c

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index f35fd3379a9406aaba60c730e8b8351a000d701f..e6c21176125b74ce95c08ce7d0c8f2b655f635cb 100644 (file)
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -26,19 +26,13 @@ enum {
 #define SH_PFC_PIN_CFG_PULL_DOWN       (1 << 3)
 #define SH_PFC_PIN_CFG_PULL_UP_DOWN    (SH_PFC_PIN_CFG_PULL_UP | \
                                         SH_PFC_PIN_CFG_PULL_DOWN)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE      (1 << 4)
-#define SH_PFC_PIN_CFG_DRIVE_STRENGTH  (1 << 5)
 
-#define SH_PFC_PIN_VOLTAGE_18_33       (0 << 6)
-#define SH_PFC_PIN_VOLTAGE_25_33       (1 << 6)
-#define SH_PFC_PIN_VOLTAGE_18_25       (2 << 6)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25        (1 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33        (2 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33        (3 << 4)
 
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33        (SH_PFC_PIN_CFG_IO_VOLTAGE | \
-                                        SH_PFC_PIN_VOLTAGE_18_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33        (SH_PFC_PIN_CFG_IO_VOLTAGE | \
-                                        SH_PFC_PIN_VOLTAGE_25_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25        (SH_PFC_PIN_CFG_IO_VOLTAGE | \
-                                        SH_PFC_PIN_VOLTAGE_18_25)
+#define SH_PFC_PIN_CFG_DRIVE_STRENGTH  (1 << 6)
 
 #define SH_PFC_PIN_CFG_NO_GPIO         (1 << 31)
 
@@ -302,7 +296,6 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77950_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77961_pinmux_info;

diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
index f2ae1c6a82dd69e6b153ad50971f4d0b608a2bc6..c34be5624954b7b79d25981c4c1e84fc5b4d30fa 100644 (file)
--- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
 /*
  * Copyright (C) 2021 Renesas Electronics Corp.
  */

diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
index eea6ad69f0b07f450500dcbac279331161477887..ff53238585721700fc3276e8f116e8b25fd91fb2 100644 (file)
--- a/include/dt-bindings/power/r8a7795-sysc.h
+++ b/include/dt-bindings/power/r8a7795-sysc.h
@@ -30,7 +30,6 @@
 #define R8A7795_PD_CA53_SCU            21
 #define R8A7795_PD_3DG_E               22
 #define R8A7795_PD_A3IR                        24
-#define R8A7795_PD_A2VC0               25      /* ES1.x only */
 #define R8A7795_PD_A2VC1               26
 
 /* Always-on power area */

diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h
index 0ec8ad727ed9a4bb628430fc1e895d49c14838c8..cde1536e9ed0e6c67701ac4b334f732cee28a25c 100644 (file)
--- a/include/dt-bindings/power/r8a779f0-sysc.h
+++ b/include/dt-bindings/power/r8a779f0-sysc.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
 /*
  * Copyright (C) 2021 Renesas Electronics Corp.
  */

diff --git a/include/linux/compat.h b/include/linux/compat.h
index 921e698f407c7deb57ad0046be6d3485c2dc1cd6..f8e3570d1ad2e5edd89d498d188d12718f0d1754 100644 (file)
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -271,6 +271,8 @@ typedef int wait_queue_head_t;
 #define __devinit
 #define __devinitdata
 #define __devinitconst
+#define __initconst
+#define __initdata
 
 #define kthread_create(...)    __builtin_return_address(0)
 #define kthread_stop(...)      do { } while (0)