Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f1712ce74d9702c7ef7069acdf938d4dfe1ca196..8d3fd54fc35cccef6c0a4f6044b13c18e973bab7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,249 @@
+2023-08-31  Andrew Pinski  <apinski@marvell.com>
+
+       PR tree-optimization/110915
+       * match.pd (min_value, max_value): Extend to vector constants.
+
+2023-08-31  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * config.in: Regenerate.
+       * config/darwin-c.cc: Change spelling to macOS.
+       * config/darwin-driver.cc: Likewise.
+       * config/darwin.h: Likewise.
+       * configure.ac: Likewise.
+       * doc/contrib.texi: Likewise.
+       * doc/extend.texi: Likewise.
+       * doc/invoke.texi: Likewise.
+       * doc/plugins.texi: Likewise.
+       * doc/tm.texi: Regenerate.
+       * doc/tm.texi.in: Change spelling to macOS.
+       * plugin.cc: Likewise.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc.
+       * config/riscv/autovec.md: Ditto.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmsac/vfnmsub
+       * config/riscv/autovec.md: Ditto.
+
+2023-08-31  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64.md (untyped_call): Emit a call_value
+       rather than a call.  List each possible destination register
+       in the call pattern.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
+       * config/riscv/autovec.md: Ditto.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+           Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+       * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc.
+       * config/riscv/autovec.md: Ditto.
+       * config/riscv/vector-iterators.md: Add UNSPEC_VFFMA.
+
+2023-08-31  Palmer Dabbelt  <palmer@rivosinc.com>
+
+       * config/riscv/autovec.md (shifts): Use
+       vector_scalar_shift_operand.
+       * config/riscv/predicates.md (vector_scalar_shift_operand): New
+       predicate.
+
+2023-08-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+       * config.gcc: Add vector cost model framework for RVV.
+       * config/riscv/riscv.cc (riscv_vectorize_create_costs): Ditto.
+       (TARGET_VECTORIZE_CREATE_COSTS): Ditto.
+       * config/riscv/t-riscv: Ditto.
+       * config/riscv/riscv-vector-costs.cc: New file.
+       * config/riscv/riscv-vector-costs.h: New file.
+
+2023-08-31  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+
+       PR target/110411
+       * config/rs6000/mma.md (define_insn_and_split movoo): Disallow
+       AltiVec address operands.
+       (define_insn_and_split movxo): Likewise.
+       * config/rs6000/predicates.md (vsx_quad_dform_memory_operand): Remove
+       redundant mode size check.
+
+2023-08-31  Lehua Ding  <lehua.ding@rivai.ai>
+
+       * config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here.
+       * config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx):
+       Change to default policy.
+       * config/riscv/riscv-vector-builtins-bases.cc: Change to default policy.
+       * config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete.
+       * config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to test.
+
+2023-08-31  Lehua Ding  <lehua.ding@rivai.ai>
+
+       * config/riscv/autovec-opt.md: Adjust.
+       * config/riscv/autovec-vls.md: Ditto.
+       * config/riscv/autovec.md: Ditto.
+       * config/riscv/riscv-protos.h (enum insn_type): Add insn_type.
+       (enum insn_flags): Add insn flags.
+       (emit_vlmax_insn): Adjust.
+       (emit_vlmax_fp_insn): Delete.
+       (emit_vlmax_ternary_insn): Delete.
+       (emit_vlmax_fp_ternary_insn): Delete.
+       (emit_nonvlmax_insn): Adjust.
+       (emit_vlmax_slide_insn): Delete.
+       (emit_nonvlmax_slide_tu_insn): Delete.
+       (emit_vlmax_merge_insn): Delete.
+       (emit_vlmax_cmp_insn): Delete.
+       (emit_vlmax_cmp_mu_insn): Delete.
+       (emit_vlmax_masked_mu_insn): Delete.
+       (emit_scalar_move_insn): Delete.
+       (emit_nonvlmax_integer_move_insn): Delete.
+       (emit_vlmax_insn_lra): Add.
+       * config/riscv/riscv-v.cc (get_mask_mode_from_insn_flags): New.
+       (emit_vlmax_insn): Adjust.
+       (emit_nonvlmax_insn): Adjust.
+       (emit_vlmax_insn_lra): Add.
+       (emit_vlmax_fp_insn): Delete.
+       (emit_vlmax_ternary_insn): Delete.
+       (emit_vlmax_fp_ternary_insn): Delete.
+       (emit_vlmax_slide_insn): Delete.
+       (emit_nonvlmax_slide_tu_insn): Delete.
+       (emit_nonvlmax_slide_insn): Delete.
+       (emit_vlmax_merge_insn): Delete.
+       (emit_vlmax_cmp_insn): Delete.
+       (emit_vlmax_cmp_mu_insn): Delete.
+       (emit_vlmax_masked_insn): Delete.
+       (emit_nonvlmax_masked_insn): Delete.
+       (emit_vlmax_masked_store_insn): Delete.
+       (emit_nonvlmax_masked_store_insn): Delete.
+       (emit_vlmax_masked_mu_insn): Delete.
+       (emit_vlmax_masked_fp_mu_insn): Delete.
+       (emit_nonvlmax_tu_insn): Delete.
+       (emit_nonvlmax_fp_tu_insn): Delete.
+       (emit_nonvlmax_tumu_insn): Delete.
+       (emit_nonvlmax_fp_tumu_insn): Delete.
+       (emit_scalar_move_insn): Delete.
+       (emit_cpop_insn): Delete.
+       (emit_vlmax_integer_move_insn): Delete.
+       (emit_nonvlmax_integer_move_insn): Delete.
+       (emit_vlmax_gather_insn): Delete.
+       (emit_vlmax_masked_gather_mu_insn): Delete.
+       (emit_vlmax_compress_insn): Delete.
+       (emit_nonvlmax_compress_insn): Delete.
+       (emit_vlmax_reduction_insn): Delete.
+       (emit_vlmax_fp_reduction_insn): Delete.
+       (emit_nonvlmax_fp_reduction_insn): Delete.
+       (expand_vec_series): Adjust.
+       (expand_const_vector): Adjust.
+       (legitimize_move): Adjust.
+       (sew64_scalar_helper): Adjust.
+       (expand_tuple_move): Adjust.
+       (expand_vector_init_insert_elems): Adjust.
+       (expand_vector_init_merge_repeating_sequence): Adjust.
+       (expand_vec_cmp): Adjust.
+       (expand_vec_cmp_float): Adjust.
+       (expand_vec_perm): Adjust.
+       (shuffle_merge_patterns): Adjust.
+       (shuffle_compress_patterns): Adjust.
+       (shuffle_decompress_patterns): Adjust.
+       (expand_load_store): Adjust.
+       (expand_cond_len_op): Adjust.
+       (expand_cond_len_unop): Adjust.
+       (expand_cond_len_binop): Adjust.
+       (expand_gather_scatter): Adjust.
+       (expand_cond_len_ternop): Adjust.
+       (expand_reduction): Adjust.
+       (expand_lanes_load_store): Adjust.
+       (expand_fold_extract_last): Adjust.
+       * config/riscv/riscv.cc (vector_zero_call_used_regs): Adjust.
+       * config/riscv/vector.md: Adjust.
+
+2023-08-31  Haochen Gui  <guihaoc@gcc.gnu.org>
+
+       PR target/96762
+       * config/rs6000/rs6000-string.cc (expand_block_move): Call vector
+       load/store with length only on 64-bit Power10.
+
+2023-08-31  Claudiu Zissulescu  <claziss@gmail.com>
+
+       * config/arc/arc.cc (arc_split_mov_const): Use LSL16 only when
+       SWAP option is enabled.
+       * config/arc/arc.md (ashlsi2_cnt16): Likewise.
+
+2023-08-31  Stamatis Markianos-Wright  <stam.markianos-wright@arm.com>
+
+       * config/arm/arm-mve-builtins-base.cc (vcaddq_rot90, vcaddq_rot270):
+       Use common insn for signed and unsigned front-end definitions.
+       * config/arm/arm_mve_builtins.def
+       (vcaddq_rot90_m_u, vcaddq_rot270_m_u): Make common.
+       (vcaddq_rot90_m_s, vcaddq_rot270_m_s): Remove.
+       * config/arm/iterators.md (mve_insn): Merge signed and unsigned defs.
+       (isu): Likewise.
+       (rot): Likewise.
+       (mve_rot): Likewise.
+       (supf): Likewise.
+       (VxCADDQ_M): Likewise.
+       * config/arm/unspecs.md (unspec): Likewise.
+       * config/arm/mve.md: Fix minor typo.
+
+2023-08-31  liuhongt  <hongtao.liu@intel.com>
+
+       * config/i386/sse.md (<avx512>_blendm<mode>): Merge
+       VF_AVX512HFBFVL into VI12HFBF_AVX512VL.
+       (VF_AVX512HFBF16): Renamed to VHFBF.
+       (VF_AVX512FP16VL): Renamed to VHF_AVX512VL.
+       (VF_AVX512FP16): Removed.
+       (div<mode>3): Adjust VF_AVX512FP16VL to VHF_AVX512VL.
+       (avx512fp16_rcp<mode>2<mask_name>): Ditto.
+       (rsqrt<mode>2): Ditto.
+       (<sse>_rsqrt<mode>2<mask_name>): Ditto.
+       (vcond<mode><code>): Ditto.
+       (vcond<sseintvecmodelower><mode>): Ditto.
+       (<avx512>_fmaddc_<mode>_mask1<round_expand_name>): Ditto.
+       (<avx512>_fmaddc_<mode>_maskz<round_expand_name>): Ditto.
+       (<avx512>_fcmaddc_<mode>_mask1<round_expand_name>): Ditto.
+       (<avx512>_fcmaddc_<mode>_maskz<round_expand_name>): Ditto.
+       (cmla<conj_op><mode>4): Ditto.
+       (fma_<mode>_fadd_fmul): Ditto.
+       (fma_<mode>_fadd_fcmul): Ditto.
+       (fma_<complexopname>_<mode>_fma_zero): Ditto.
+       (fma_<mode>_fmaddc_bcst): Ditto.
+       (fma_<mode>_fcmaddc_bcst): Ditto.
+       (<avx512>_<complexopname>_<mode>_mask<round_name>): Ditto.
+       (cmul<conj_op><mode>3): Ditto.
+       (<avx512>_<complexopname>_<mode><maskc_name><round_name>):
+       Ditto.
+       (vec_unpacks_lo_<mode>): Ditto.
+       (vec_unpacks_hi_<mode>): Ditto.
+       (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto.
+       (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto.
+       (*vec_extract<mode>_0): Ditto.
+       (*<avx512>_cmp<mode>3): Extend to V48H_AVX512VL.
+
+2023-08-31  Lehua Ding  <lehua.ding@rivai.ai>
+
+       PR target/111234
+       * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
+
+2023-08-31  Jiufu Guo  <guojiufu@linux.ibm.com>
+
+       * range-op-mixed.h (operator_plus::overflow_free_p): New declare.
+       (operator_minus::overflow_free_p): New declare.
+       (operator_mult::overflow_free_p): New declare.
+       * range-op.cc (range_op_handler::overflow_free_p): New function.
+       (range_operator::overflow_free_p): New default function.
+       (operator_plus::overflow_free_p): New function.
+       (operator_minus::overflow_free_p): New function.
+       (operator_mult::overflow_free_p): New function.
+       * range-op.h (range_op_handler::overflow_free_p): New declare.
+       (range_operator::overflow_free_p): New declare.
+       * value-range.cc (irange::nonnegative_p): New function.
+       (irange::nonpositive_p): New function.
+       * value-range.h (irange::nonnegative_p): New declare.
+       (irange::nonpositive_p): New declare.
+
 2023-08-30  Dimitar Dimitrov  <dimitar@dinux.eu>
 
        PR target/106562

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 86bc2a9aa08344bef30bac8e5eed63d116801e54..5e591a05e966c57423d14b6da93e4c6c2afd574f 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230831
+20230901

diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog
index b113b414447029233ab6685d44d45a440fe74133..2622c29f46cbd896a0d034394408bca11b616344 100644 (file)
--- a/gcc/analyzer/ChangeLog
+++ b/gcc/analyzer/ChangeLog
@@ -1,3 +1,7 @@
+2023-08-31  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * kf.cc: Change spelling to macOS.
+
 2023-08-30  Eric Feng  <ef2648@columbia.edu>
 
        PR analyzer/107646

diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 0ff87ef807fa1683f53bceddd5f06742cc22baf2..2ae494ee2b9f7326aabb5effb15b9ad1c71737ce 100644 (file)
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,13 @@
+2023-08-31  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * c.opt: Change spelling to macOS.
+
+2023-08-31  Richard Biener  <rguenther@suse.de>
+
+       PR middle-end/111253
+       * c-pretty-print.cc (c_pretty_printer::primary_expression):
+       Only dump gimple_assign_single_p SSA def RHS.
+
 2023-08-25  Sandra Loosemore  <sandra@codesourcery.com>
 
        * c-common.h (c_omp_check_loop_binding_exprs): Declare.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index e11ed91eb0ed5a0ef7964ed5bd20ee5fe674b442..c7195948f07068837152903325143c4ecf14c857 100644 (file)
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,7 @@
+2023-08-31  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * gfortran.texi: Likewise.
+
 2023-08-30  Mikael Morin  <mikael@gcc.gnu.org>
 
        PR fortran/48776

diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog
index 38e71c98df23ca2949001617053196026847f514..1e60eaef5aeb059e7672625740593dfc935533f2 100644 (file)
--- a/gcc/jit/ChangeLog
+++ b/gcc/jit/ChangeLog
@@ -1,3 +1,7 @@
+2023-08-31  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * jit-playback.cc: Change spelling to macOS.
+
 2023-08-29  Guillaume Gomez  <guillaume1.gomez@gmail.com>
 
        * docs/topics/compatibility.rst: Add documentation for LIBGCCJIT_ABI_25.

diff --git a/gcc/objc/ChangeLog b/gcc/objc/ChangeLog
index 0d96523b880feeb51950d660cc98e8b91813ef98..155efd18df2df2c0a9951a1cad3261f3b75dfe44 100644 (file)
--- a/gcc/objc/ChangeLog
+++ b/gcc/objc/ChangeLog
@@ -1,3 +1,7 @@
+2023-08-31  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * objc-act.cc: Change spelling to macOS.
+
 2023-05-18  Bernhard Reutner-Fischer  <aldot@gcc.gnu.org>
 
        * objc-act.cc (objc_volatilize_decl): Use _P() defines from tree.h.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a2c63cb4fc06f7a2e8247fdb86428dee39a89dc4..f97bb3c9f20f62924049f71001c49e642aaff2b7 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,86 @@
+2023-08-31  Andrew Pinski  <apinski@marvell.com>
+
+       PR tree-optimization/110915
+       * gcc.dg/pr110915-1.c: New test.
+       * gcc.dg/pr110915-10.c: New test.
+       * gcc.dg/pr110915-11.c: New test.
+       * gcc.dg/pr110915-12.c: New test.
+       * gcc.dg/pr110915-2.c: New test.
+       * gcc.dg/pr110915-3.c: New test.
+       * gcc.dg/pr110915-4.c: New test.
+       * gcc.dg/pr110915-5.c: New test.
+       * gcc.dg/pr110915-6.c: New test.
+       * gcc.dg/pr110915-7.c: New test.
+       * gcc.dg/pr110915-8.c: New test.
+       * gcc.dg/pr110915-9.c: New test.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: New test.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: New test.
+
+2023-08-31  Peter Bergner  <bergner@linux.ibm.com>
+
+       PR testsuite/111228
+       * gcc.target/powerpc/fold-vec-logical-ors-char.c: Update instruction
+       counts to match the number of associated vec_* built-in calls.
+       * gcc.target/powerpc/fold-vec-logical-ors-int.c: Likewise.
+       * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: Likewise.
+       * gcc.target/powerpc/fold-vec-logical-ors-short.c: Likewise.
+       * gcc.target/powerpc/fold-vec-logical-other-char.c: Likewise.
+       * gcc.target/powerpc/fold-vec-logical-other-int.c: Likewise.
+       * gcc.target/powerpc/fold-vec-logical-other-longlong.c: Likewise.
+       * gcc.target/powerpc/fold-vec-logical-other-short.c: Likewise.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test.
+
+2023-08-31  Pan Li  <pan2.li@intel.com>
+           Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+       * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: New test.
+
+2023-08-31  Richard Biener  <rguenther@suse.de>
+
+       PR middle-end/111253
+       * gcc.dg/Wfree-nonheap-object-7.c: New testcase.
+
+2023-08-31  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+
+       PR target/110411
+       * gcc.target/powerpc/pr110411-1.c: New testcase.
+       * gcc.target/powerpc/pr110411-2.c: New testcase.
+
+2023-08-31  Lehua Ding  <lehua.ding@rivai.ai>
+
+       * gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Adjust.
+       * gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Adjust.
+       * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: New test.
+
+2023-08-31  Richard Biener  <rguenther@suse.de>
+
+       * gcc.dg/tree-ssa/forwprop-42.c: Move ...
+       * gcc.target/i386/pr111228.c: ... here.  Enable SSE2.
+
+2023-08-31  Richard Biener  <rguenther@suse.de>
+
+       * gcc.target/i386/pr52252-atom.c: Add -mprefer-vector-width=128.
+       * gcc.target/i386/pr52252-core.c: Likewise.
+
+2023-08-31  Haochen Gui  <guihaoc@gcc.gnu.org>
+
+       PR target/96762
+       * gcc.target/powerpc/pr96762.c: New.
+
+2023-08-31  Lehua Ding  <lehua.ding@rivai.ai>
+
+       PR target/111234
+       * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
+
 2023-08-30  Eric Feng  <ef2648@columbia.edu>
 
        PR analyzer/107646