+2004-11-16 Eric Christopher <echristo@redhat.com>
+
+ * config/mips/mips.c: Use rtl _P predicates.
+ * config/mips/mips.h: Ditto.
+ * config/mips/mips.md: Ditto.
+
2004-11-16 Fariborz Jahanian <fjahanian@apple.com>
* config/rs6000/altivec.md (altivec_vandc): Canonicalize
* gcc/cse.c (struct change_cc_mode_args): New structure.
(cse_change_cc_mode_insn): New function.
(cse_change_cc_mode): Use validate_change to perfom changes.
- (cse_change_cc_mode_insns, cse_condition_code_reg):
+ (cse_change_cc_mode_insns, cse_condition_code_reg):
Call cse_change_cc_mode_insn.
2004-11-16 Steven Bosscher <stevenb@suse.de>
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
- return (GET_CODE (x) == REG
+ return (REG_P (x)
&& mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
}
int
mips_fetch_insns (rtx x)
{
- gcc_assert (GET_CODE (x) == MEM);
+ gcc_assert (MEM_P (x));
return mips_address_insns (XEXP (x, 0), GET_MODE (x));
}
else
count += 2;
}
-
+
if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
count++;
return count;
else
byte = 0;
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
{
if (FP_REG_P (REGNO (op)))
return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
}
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
return simplify_gen_subreg (word_mode, op, mode, byte);
ldc1 and sdc1 on MIPS II and above. */
if (mips_isa > 1)
{
- if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
+ if (FP_REG_RTX_P (dest) && MEM_P (src))
return false;
- if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
+ if (FP_REG_RTX_P (src) && MEM_P (dest))
return false;
}
return true;
rtx low_dest;
low_dest = mips_subword (dest, 0);
- if (GET_CODE (low_dest) == REG
+ if (REG_P (low_dest)
&& reg_overlap_mentioned_p (low_dest, src))
{
emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
rtx fp1, fp2;
/* Change the source to SFmode. */
- if (GET_CODE (src) == MEM)
+ if (MEM_P (src))
src = adjust_address (src, SFmode, 0);
- else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
+ else if (REG_P (src) || GET_CODE (src) == SUBREG)
src = gen_rtx_REG (SFmode, true_regnum (src));
fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
/* Check that the operand really is a MEM. Not all the extv and
extzv predicates are checked. */
- if (GET_CODE (*op) != MEM)
+ if (!MEM_P (*op))
return false;
/* Check that the size is valid. */
int regno = -1;
int gp_reg_p;
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x)|| GET_CODE (x) == SUBREG)
regno = true_regnum (x);
gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
if (class == FP_REGS)
{
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
{
/* In this case we can use lwc1, swc1, ldc1 or sdc1. */
return NO_REGS;
/* We need to emit the initialization after the FUNCTION_BEG
note, so that it will be integrated. */
for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
- if (GET_CODE (scan) == NOTE
+ if (NOTE_P (scan)
&& NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
break;
if (scan == NULL_RTX)
static int
mips16_insn_length (rtx insn)
{
- if (GET_CODE (insn) == JUMP_INSN)
+ if (JUMP_P (insn))
{
rtx body = PATTERN (insn);
if (GET_CODE (body) == ADDR_VEC)
first = SEQ_BEGIN (insn);
second = SEQ_END (insn);
- if (GET_CODE (first) == JUMP_INSN
- && GET_CODE (second) == INSN
+ if (JUMP_P (first)
+ && NONJUMP_INSN_P (second)
&& GET_CODE (PATTERN (first)) == SET
&& GET_CODE (SET_DEST (PATTERN (first))) == PC
&& GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
way, if the nop makes Y aligned, it will also align any labels
between X and Y. */
if (state.insns_left != state.issue_rate
- && GET_CODE (subinsn) != CALL_INSN)
+ && !CALL_P (subinsn))
{
if (subinsn == SEQ_BEGIN (insn) && aligned_p)
{
mips.md patern, the length is only an estimate. Insert an
8 byte alignment after it so that the following instructions
can be handled correctly. */
- if (GET_CODE (SEQ_BEGIN (insn)) == INSN
+ if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
&& (recog_memoized (insn) < 0 || length >= 8))
{
next = emit_insn_after (gen_align (GEN_INT (3)), insn);
enum mips_fp_condition cond;
/* The name of the builtin function. */
- const char *name;
+ const char *name;
/* Specifies how the function should be expanded. */
enum mips_builtin_type builtin_type;
#define ALL_COP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
-#define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
+#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
to initialize the mips16 gp pseudo register. */
#define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
(((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
- : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
+ : ((CODE) == 'R') ? (MEM_P (OP) \
&& mips_fetch_insns (OP) == 1) \
: ((CODE) == 'S') ? (CONSTANT_P (OP) \
&& call_insn_operand (OP, VOIDmode)) \
: ((CODE) == 'U') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
&& !mips_dangerous_for_la25_p (OP)) \
- : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
+ : ((CODE) == 'W') ? (MEM_P (OP) \
&& memory_operand (OP, VOIDmode) \
&& (!TARGET_MIPS16 \
|| (!stack_operand (OP, VOIDmode) \
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0x7f
(plus:SI (match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
&& GET_CODE (operands[2]) == CONST_INT
(plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0xf
(plus:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
&& GET_CODE (operands[2]) == CONST_INT
(match_operand:DI 1 "const_int_operand"))))]
"TARGET_64BIT && TARGET_MIPS16 && reload_completed
&& !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
(mem:SI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
[(set (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) >= 0x100
(mem:HI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
(mem:QI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0