sparc64: flush translations on mmu context change

- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers
  using value of DMMU primary and secondary context registers, so we need to
  flush softmmu translations when context registers are changed

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 28224b23dc62af6f475c005242f0cf9226331b57..edeeb4469a8334e7cfaa6145e8b50b6f148a29e5 100644 (file)
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -2959,9 +2959,15 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
                 break;
             case 1: // Primary context
                 env->dmmu.mmu_primary_context = val;
+                /* can be optimized to only flush MMU_USER_IDX
+                   and MMU_KERNEL_IDX entries */
+                tlb_flush(env, 1);
                 break;
             case 2: // Secondary context
                 env->dmmu.mmu_secondary_context = val;
+                /* can be optimized to only flush MMU_USER_SECONDARY_IDX
+                   and MMU_KERNEL_SECONDARY_IDX entries */
+                tlb_flush(env, 1);
                 break;
             case 5: // TSB access
                 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"