--- /dev/null
+From 18932a28419596bc9403770f5d8a108c5433fe59 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Apr 2013 13:55:15 -0400
+Subject: drm/radeon: add some new SI PCI ids
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 18932a28419596bc9403770f5d8a108c5433fe59 upstream.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/drm/drm_pciids.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -231,6 +231,7 @@
+ {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -238,11 +239,13 @@
+ {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
--- /dev/null
+From 7c1c7c18fc752b2a1d07597286467ef186312463 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 5 Apr 2013 10:28:08 -0400
+Subject: drm/radeon/dce6: add missing display reg for tiling setup
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream.
+
+A new tiling config register for the display blocks was
+added on DCE6.
+
+May fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=62889
+https://bugs.freedesktop.org/show_bug.cgi?id=57919
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ni.c | 2 ++
+ drivers/gpu/drm/radeon/nid.h | 4 ++++
+ drivers/gpu/drm/radeon/si.c | 1 +
+ drivers/gpu/drm/radeon/sid.h | 2 ++
+ 4 files changed, 9 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -911,6 +911,8 @@ static void cayman_gpu_init(struct radeo
+ WREG32(GB_BACKEND_MAP, gb_backend_map);
+ WREG32(GB_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
++ if (ASIC_IS_DCE6(rdev))
++ WREG32(DMIF_ADDR_CALC, gb_addr_config);
+ WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+
+ /* primary versions */
+--- a/drivers/gpu/drm/radeon/nid.h
++++ b/drivers/gpu/drm/radeon/nid.h
+@@ -42,6 +42,10 @@
+ #define CAYMAN_MAX_TCC_MASK 0xFF
+
+ #define DMIF_ADDR_CONFIG 0xBD4
++
++/* DCE6 only */
++#define DMIF_ADDR_CALC 0xC00
++
+ #define SRBM_GFX_CNTL 0x0E44
+ #define RINGID(x) (((x) & 0x3) << 0)
+ #define VMID(x) (((x) & 0x7) << 0)
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -1799,6 +1799,7 @@ static void si_gpu_init(struct radeon_de
+ rdev->config.si.backend_map = gb_backend_map;
+ WREG32(GB_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
++ WREG32(DMIF_ADDR_CALC, gb_addr_config);
+ WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+
+ /* primary versions */
+--- a/drivers/gpu/drm/radeon/sid.h
++++ b/drivers/gpu/drm/radeon/sid.h
+@@ -55,6 +55,8 @@
+
+ #define DMIF_ADDR_CONFIG 0xBD4
+
++#define DMIF_ADDR_CALC 0xC00
++
+ #define SRBM_STATUS 0xE50
+
+ #define CC_SYS_RB_BACKEND_DISABLE 0xe80
--- /dev/null
+From abf1457bbbe4c62066bd03c6d31837dea28644dc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 10 Apr 2013 19:08:14 -0400
+Subject: drm/radeon: disable the crtcs in mc_stop (evergreen+) (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit abf1457bbbe4c62066bd03c6d31837dea28644dc upstream.
+
+Just disabling the mem requests should be enough, but
+that doesn't seem to work correctly on efi systems.
+
+May fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=57567
+https://bugs.freedesktop.org/show_bug.cgi?id=43655
+https://bugzilla.kernel.org/show_bug.cgi?id=56441
+
+v2: blank displays first, then disable.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1146,6 +1146,7 @@ void evergreen_mc_stop(struct radeon_dev
+ tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
+ radeon_wait_for_vblank(rdev, i);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
+ }
+@@ -1153,8 +1154,10 @@ void evergreen_mc_stop(struct radeon_dev
+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
+ radeon_wait_for_vblank(rdev, i);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ }
+ /* wait for the next frame */
+@@ -1164,6 +1167,15 @@ void evergreen_mc_stop(struct radeon_dev
+ break;
+ udelay(1);
+ }
++
++ /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
++ tmp &= ~EVERGREEN_CRTC_MASTER_EN;
++ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++ save->crtc_enabled[i] = false;
++ /* ***** */
+ } else {
+ save->crtc_enabled[i] = false;
+ }
--- /dev/null
+From bf05d9985111f85ed6922c134567b96eb789283b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 18 Mar 2013 17:12:50 -0400
+Subject: drm/radeon: don't use get_engine_clock() on APUs
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit bf05d9985111f85ed6922c134567b96eb789283b upstream.
+
+It doesn't work reliably. Just report back the currently
+selected engine clock.
+
+Partially fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=62493
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_pm.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -872,7 +872,11 @@ static int radeon_debugfs_pm_info(struct
+ struct radeon_device *rdev = dev->dev_private;
+
+ seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
+- seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
++ /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
++ if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
++ seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
++ else
++ seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
+ seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
+ if (rdev->asic->pm.get_memory_clock)
+ seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
--- /dev/null
+From 968c01664ccbe0e46c19a1af662c4c266a904203 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 10 Apr 2013 09:58:42 -0400
+Subject: drm/radeon: properly lock disp in mc_stop/resume for evergreen+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 968c01664ccbe0e46c19a1af662c4c266a904203 upstream.
+
+Need to wait for the new addresses to take affect before
+re-enabling the MC.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 47 ++++++++++++++++++++++++++++++---
+ drivers/gpu/drm/radeon/evergreen_reg.h | 2 +
+ 2 files changed, 45 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1147,18 +1147,14 @@ void evergreen_mc_stop(struct radeon_dev
+ if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
+ radeon_wait_for_vblank(rdev, i);
+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ } else {
+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
+ radeon_wait_for_vblank(rdev, i);
+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ }
+ /* wait for the next frame */
+@@ -1185,6 +1181,22 @@ void evergreen_mc_stop(struct radeon_dev
+ }
+ /* wait for the MC to settle */
+ udelay(100);
++
++ /* lock double buffered regs */
++ for (i = 0; i < rdev->num_crtc; i++) {
++ if (save->crtc_enabled[i]) {
++ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
++ if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
++ tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
++ WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++ if (!(tmp & 1)) {
++ tmp |= 1;
++ WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++ }
++ }
++ }
+ }
+
+ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
+@@ -1206,6 +1218,33 @@ void evergreen_mc_resume(struct radeon_d
+ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
+ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
+
++ /* unlock regs and wait for update */
++ for (i = 0; i < rdev->num_crtc; i++) {
++ if (save->crtc_enabled[i]) {
++ tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
++ if ((tmp & 0x3) != 0) {
++ tmp &= ~0x3;
++ WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
++ if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
++ tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
++ WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++ if (tmp & 1) {
++ tmp &= ~1;
++ WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++ }
++ for (j = 0; j < rdev->usec_timeout; j++) {
++ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
++ if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
++ break;
++ udelay(1);
++ }
++ }
++ }
++
+ /* unblackout the MC */
+ tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
+ tmp &= ~BLACKOUT_MODE_MASK;
+--- a/drivers/gpu/drm/radeon/evergreen_reg.h
++++ b/drivers/gpu/drm/radeon/evergreen_reg.h
+@@ -225,6 +225,8 @@
+ #define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
+ #define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
+ #define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
++#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4
++#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
+
+ #define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
+ #define EVERGREEN_DC_GPIO_HPD_A 0x64b4
cpufreq-longhaul-disable-driver-by-default.patch
drm-i915-add-no-lvds-quirk-for-fujitsu-esprimo-q900.patch
drm-i915-fall-back-to-bit-banging-mode-for-dvo-transmitter-detection.patch
+drm-radeon-don-t-use-get_engine_clock-on-apus.patch
+drm-radeon-dce6-add-missing-display-reg-for-tiling-setup.patch
+drm-radeon-properly-lock-disp-in-mc_stop-resume-for-evergreen.patch
+drm-radeon-disable-the-crtcs-in-mc_stop-evergreen-v2.patch
+drm-radeon-add-some-new-si-pci-ids.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
