arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j

RK3588j is the 'industrial' variant of RK3588, and it uses a different
set of OPPs both in terms of allowed frequencies and in terms of
applicable voltages at each frequency setpoint.

Add the OPPs that apply to RK3588j (and apparently RK3588m too) to
enable dynamic CPU frequency scaling.

OPP values are derived from Rockchip downstream sources [1] by taking
only those OPPs which have the highest frequency for a given voltage
level and dropping the rest (if they are included, the kernel complains
at boot time about them being inefficient)

[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
index 0bbeee399a63bb5481286f9115ef601ed758308a..b7e69553857b12ddd17ace905a20def9cb822d34 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
@@ -5,3 +5,111 @@
  */
 
 #include "rk3588-extra.dtsi"
+
+/ {
+       cluster0_opp_table: opp-table-cluster0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <750000 750000 950000>;
+                       clock-latency-ns = <40000>;
+                       opp-suspend;
+               };
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <887500 887500 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1704000000 {
+                       opp-hz = /bits/ 64 <1704000000>;
+                       opp-microvolt = <937500 937500 950000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+
+       cluster1_opp_table: opp-table-cluster1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <750000 750000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <787500 787500 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <875000 875000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2016000000 {
+                       opp-hz = /bits/ 64 <2016000000>;
+                       opp-microvolt = <950000 950000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+
+       cluster2_opp_table: opp-table-cluster2 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <750000 750000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <787500 787500 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <875000 875000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2016000000 {
+                       opp-hz = /bits/ 64 <2016000000>;
+                       opp-microvolt = <950000 950000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+};
+
+&cpu_b0 {
+       operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b1 {
+       operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b2 {
+       operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_b3 {
+       operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_l0 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l1 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l2 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l3 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};