clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC

Add clock and reset entries for the DSI and LCDC peripherals.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251015192611.241920-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index dce5755d85ec1af88fdf1871b14174e894012bc3..c9f6d91884c39b404aab353beb5f7dca893ddea2 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/renesas.h>
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -30,6 +31,7 @@ enum clk_ids {
        CLK_PLLCA55,
        CLK_PLLVDO,
        CLK_PLLETH,
+       CLK_PLLDSI,
        CLK_PLLGPU,
 
        /* Internal Core Clocks */
@@ -64,6 +66,9 @@ enum clk_ids {
        CLK_SMUX2_GBE0_RXCLK,
        CLK_SMUX2_GBE1_TXCLK,
        CLK_SMUX2_GBE1_RXCLK,
+       CLK_CDIV4_PLLETH_LPCLK,
+       CLK_PLLETH_LPCLK_GEAR,
+       CLK_PLLDSI_GEAR,
        CLK_PLLGPU_GEAR,
 
        /* Module Clocks */
@@ -92,6 +97,26 @@ static const struct clk_div_table dtable_2_16[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_2_32[] = {
+       {0, 2},
+       {1, 4},
+       {2, 6},
+       {3, 8},
+       {4, 10},
+       {5, 12},
+       {6, 14},
+       {7, 16},
+       {8, 18},
+       {9, 20},
+       {10, 22},
+       {11, 24},
+       {12, 26},
+       {13, 28},
+       {14, 30},
+       {15, 32},
+       {0, 0},
+};
+
 static const struct clk_div_table dtable_2_64[] = {
        {0, 2},
        {1, 4},
@@ -108,6 +133,17 @@ static const struct clk_div_table dtable_2_100[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_16_128[] = {
+       {0, 16},
+       {1, 32},
+       {2, 64},
+       {3, 128},
+       {0, 0},
+};
+
+RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
+#define PLLDSI         PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2h_cpg_pll_dsi_limits)
+
 /* Mux clock tables */
 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@@ -129,6 +165,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
        DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
        DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
+       DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
        DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
 
        /* Internal Core Clocks */
@@ -170,6 +207,12 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
        DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
        DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
+       DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
+       DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
+                 CSDIV0_DIVCTL2, dtable_16_128),
+
+       DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
+                      CSDIV1_DIVCTL2, dtable_2_32),
 
        DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
 
@@ -383,6 +426,22 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(9))),
        DEF_MOD("isp_0_isp_sclk",               CLK_PLLVDO_ISP, 14, 5, 7, 5,
                                                BUS_MSTOP(9, BIT(9))),
+       DEF_MOD("dsi_0_pclk",                   CLK_PLLDTY_DIV16, 14, 8, 7, 8,
+                                               BUS_MSTOP(9, BIT(14) | BIT(15))),
+       DEF_MOD("dsi_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
+                                               BUS_MSTOP(9, BIT(14) | BIT(15))),
+       DEF_MOD("dsi_0_vclk1",                  CLK_PLLDSI_GEAR, 14, 10, 7, 10,
+                                               BUS_MSTOP(9, BIT(14) | BIT(15))),
+       DEF_MOD("dsi_0_lpclk",                  CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
+                                               BUS_MSTOP(9, BIT(14) | BIT(15))),
+       DEF_MOD("dsi_0_pllref_clk",             CLK_QEXTAL, 14, 12, 7, 12,
+                                               BUS_MSTOP(9, BIT(14) | BIT(15))),
+       DEF_MOD("lcdc_0_clk_a",                 CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
+                                               BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
+       DEF_MOD("lcdc_0_clk_p",                 CLK_PLLDTY_DIV16, 14, 14, 7, 14,
+                                               BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
+       DEF_MOD("lcdc_0_clk_d",                 CLK_PLLDSI_GEAR, 14, 15, 7, 15,
+                                               BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
        DEF_MOD("gpu_0_clk",                    CLK_PLLGPU_GEAR, 15, 0, 7, 16,
                                                BUS_MSTOP(3, BIT(4))),
        DEF_MOD("gpu_0_axi_clk",                CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -464,6 +523,9 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(13, 2, 6, 3),           /* ISP_0_REG_ARESETN */
        DEF_RST(13, 3, 6, 4),           /* ISP_0_ISP_SRESETN */
        DEF_RST(13, 4, 6, 5),           /* ISP_0_PRESETN */
+       DEF_RST(13, 7, 6, 8),           /* DSI_0_PRESETN */
+       DEF_RST(13, 8, 6, 9),           /* DSI_0_ARESETN */
+       DEF_RST(13, 12, 6, 13),         /* LCDC_0_RESET_N */
        DEF_RST(13, 13, 6, 14),         /* GPU_0_RESETN */
        DEF_RST(13, 14, 6, 15),         /* GPU_0_AXI_RESETN */
        DEF_RST(13, 15, 6, 16),         /* GPU_0_ACE_RESETN */

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index f7b4e4785d0f78942c1d559dc09a18501b2abde0..dc957bdaf5e9715891f08e7c36b58d70da1582c7 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -127,6 +127,7 @@ struct fixed_mod_conf {
 #define CPG_CDDIV3             (0x40C)
 #define CPG_CDDIV4             (0x410)
 #define CPG_CSDIV0             (0x500)
+#define CPG_CSDIV1             (0x504)
 
 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
 #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
@@ -144,7 +145,9 @@ struct fixed_mod_conf {
 
 #define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
 #define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
+#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
 #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
+#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
 
 #define SSEL0_SELCTL2  SMUX_PACK(CPG_SSEL0, 8, 1)
 #define SSEL0_SELCTL3  SMUX_PACK(CPG_SSEL0, 12, 1)