RISC-V: Added testcase to show the current rvc and xlen problems

diff --git a/gas/testsuite/gas/riscv/option-norvc.d b/gas/testsuite/gas/riscv/option-norvc.d
new file mode 100644 (file)
index 0000000..13b0705
--- /dev/null
+++ b/gas/testsuite/gas/riscv/option-norvc.d
@@ -0,0 +1,44 @@
+#as: -misa-spec=2.2 -march=rv64i
+#source: option-norvc.s
+#objdump: -d --syms --special-syms -Mno-aliases
+
+.*:[   ]+file format .*
+
+SYMBOL TABLE:
+0+00 l    d  .text     0+00 .text
+0+00 l    d  .data     0+00 .data
+0+00 l    d  .bss      0+00 .bss
+0+00 l       .text     0+00 \$xrv64i2p0_c2p0
+0+02 l       .text     0+00 \$xrv64i2p0
+0+06 l       .text     0+00 \$xrv32i2p0_f2p0_c2p0
+0+08 l       .text     0+00 \$xrv32i2p0_f2p0
+0+0c l       .text     0+00 \$xrv32i2p0_f2p0_d2p0_c2p0
+0+0e l       .text     0+00 \$xrv32i2p0_f2p0_d2p0
+0+12 l       .text     0+00 \$xrv32i2p0_f2p0_d2p0_zca1p0
+0+18 l       .text     0+00 \$xrv32i2p0_f2p0_zca1p0_zcf1p0
+0+1e l       .text     0+00 \$xrv32i2p0_f2p0_d2p0_zca1p0_zcd1p0
+0+24 l       .text     0+00 \$xrv32i2p0_zilsd1p0_zca1p0_zcb1p0_zclsd1p0
+0+30 l       .text     0+00 \$xrv64i2p0_zca1p0_zcmop1p0_zcmp1p0_zcmt1p0
+0+0 l    d  .riscv.attributes  0+00 .riscv.attributes
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[      ]+[0-9a-f]+:[   ]+0001[         ]+c\.addi[      ]+zero,0
+[      ]+[0-9a-f]+:[   ]+00000013[     ]+addi[         ]+zero,zero,0
+[      ]+[0-9a-f]+:[   ]+6108[         ]+c\.ld[        ]+a0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+00052507[     ]+flw[  ]+fa0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+2108[         ]+c\.fld[       ]+fa0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+00053507[     ]+fld[  ]+fa0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+0001[         ]+c\.addi[      ]+zero,0
+[      ]+[0-9a-f]+:[   ]+00000013[     ]+addi[         ]+zero,zero,0
+[      ]+[0-9a-f]+:[   ]+6108[         ]+c\.ld[        ]+a0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+00052507[     ]+flw[  ]+fa0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+2108[         ]+c\.fld[       ]+fa0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+00053507[     ]+fld[  ]+fa0,0\(a0\)
+[      ]+[0-9a-f]+:[   ]+8020[         ]+c\.lbu[       ]+s0,2\(s0\)
+[      ]+[0-9a-f]+:[   ]+6080[         ]+c\.ld[        ]+s0,0\(s1\)
+[      ]+[0-9a-f]+:[   ]+00244403[     ]+lbu[  ]+s0,2\(s0\)
+[      ]+[0-9a-f]+:[   ]+0004b403[     ]+ld[   ]+s0,0\(s1\)
+#...

diff --git a/gas/testsuite/gas/riscv/option-norvc.s b/gas/testsuite/gas/riscv/option-norvc.s
new file mode 100644 (file)
index 0000000..d4f05e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/option-norvc.s
@@ -0,0 +1,50 @@
+.option rvc
+nop
+.option norvc
+nop
+
+.option push
+.option arch, rv32i
+.option arch, +c,+f
+flw fa0, 0(a0)
+.option norvc
+flw fa0, 0(a0)
+.option pop
+
+.option arch, +c,+d
+fld fa0, 0(a0)
+.option norvc
+fld fa0, 0(a0)
+
+.option arch, +zca
+nop
+.option norvc
+nop
+
+.option push
+.option arch, rv32i
+.option arch, +zcf
+flw fa0, 0(a0)
+.option norvc
+flw fa0, 0(a0)
+.option pop
+
+.option arch, +zcd
+fld fa0, 0(a0)
+.option norvc
+fld fa0, 0(a0)
+
+.option push
+.option arch, rv32i
+.option arch, +zcb,+zclsd
+lbu x8,2(x8)
+ld x8, 0(x9)
+.option norvc
+lbu x8,2(x8)
+ld x8, 0(x9)
+.option pop
+
+.option arch, rv64i
+.option arch, +zcmp,+zcmop,+zcmt
+.option norvc
+nop