RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds the additional extension "XTheadVdot" based on the
"V" extension, and it provides four 8-bit multiply and add with
32-bit instructions for the "v" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([2]).

Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com>
[1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot
[2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add support
	for "XTheadVdot" extension.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi: Likewise.
	* testsuite/gas/riscv/march-help.l: Likewise.
	* testsuite/gas/riscv/x-thead-vdot.d: New test.
	* testsuite/gas/riscv/x-thead-vdot.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New.
	* opcode/riscv.h (enum riscv_insn_class): Add insn class for
	XTheadVdot.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 72610dc7a744c948ae973b8c33d74fa3301d2424..a2f67bc244ed583488db69bea447f584b64cc476 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1507,6 +1507,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadmempair",    ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xtheadsync",       ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xtheadvector",     ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
+  {"xtheadvdot",       ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xtheadzvamo",      ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xsfvcp",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
@@ -2806,6 +2807,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadsync");
     case INSN_CLASS_XTHEADVECTOR:
       return riscv_subset_supports (rps, "xtheadvector");
+    case INSN_CLASS_XTHEADVDOT:
+      return riscv_subset_supports (rps, "xtheadvdot");
     case INSN_CLASS_XTHEADZVAMO:
       return riscv_subset_supports (rps, "xtheadzvamo");
     case INSN_CLASS_XVENTANACONDOPS:
@@ -3111,6 +3114,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadsync";
     case INSN_CLASS_XTHEADVECTOR:
       return "xtheadvector";
+    case INSN_CLASS_XTHEADVDOT:
+      return "xtheadvdot";
     case INSN_CLASS_XTHEADZVAMO:
       return "xtheadzvamo";
     case INSN_CLASS_XSFCEASE:

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 86cea386d8c37d7c3c405bd49dcabf1e3635b668..0a92e7805ee2e8a84e753222fa1c1e7609647a22 100644 (file)
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -862,6 +862,11 @@ The XTheadVector extension provides instructions for thead vector.
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}.
 
+@item XTheadVdot
+The XTheadVdot extension provides instructions for vector dot.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}.
+
 @item XTheadZvamo
 The XTheadZvamo extension is a subextension of the XTheadVector extension,
 and it provides AMO instructions for the T-Head VECTOR vendor extension.

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index b7975ff9ade2627bc712e71a18bdce5ab3423212..f4b1e306895825e25d4177ef296c3dd7be770bee 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -160,6 +160,7 @@ All available -march extensions for RISC-V:
        xtheadmempair                           1.0
        xtheadsync                              1.0
        xtheadvector                            1.0
+       xtheadvdot                              1.0
        xtheadzvamo                             1.0
        xventanacondops                         1.0
        xsfvcp                                  1.0

diff --git a/gas/testsuite/gas/riscv/x-thead-vdot.d b/gas/testsuite/gas/riscv/x-thead-vdot.d
new file mode 100644 (file)
index 0000000..021ff1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vdot.d
@@ -0,0 +1,30 @@
+#as: -march=rv32if_xtheadvdot
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <test_int8_int4>:
+[      ]+[0-9a-f]+:[   ]+8000600b[     ]+th.vmaqa\.vv[         ]+v0,v0,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+8200600b[     ]+th.vmaqa\.vv[         ]+v0,v0,v0
+[      ]+[0-9a-f]+:[   ]+8211600b[     ]+th.vmaqa\.vv[         ]+v0,v2,v1
+[      ]+[0-9a-f]+:[   ]+8400600b[     ]+th.vmaqa\.vx[         ]+v0,zero,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+8600600b[     ]+th.vmaqa\.vx[         ]+v0,zero,v0
+[      ]+[0-9a-f]+:[   ]+8611600b[     ]+th.vmaqa\.vx[         ]+v0,sp,v1
+[      ]+[0-9a-f]+:[   ]+8800600b[     ]+th.vmaqau\.vv[        ]+v0,v0,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+8a00600b[     ]+th.vmaqau\.vv[        ]+v0,v0,v0
+[      ]+[0-9a-f]+:[   ]+8a11600b[     ]+th.vmaqau\.vv[        ]+v0,v2,v1
+[      ]+[0-9a-f]+:[   ]+8c00600b[     ]+th.vmaqau\.vx[        ]+v0,zero,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+8e00600b[     ]+th.vmaqau\.vx[        ]+v0,zero,v0
+[      ]+[0-9a-f]+:[   ]+8e11600b[     ]+th.vmaqau\.vx[        ]+v0,sp,v1
+[      ]+[0-9a-f]+:[   ]+9000600b[     ]+th.vmaqasu\.vv[       ]+v0,v0,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+9200600b[     ]+th.vmaqasu\.vv[       ]+v0,v0,v0
+[      ]+[0-9a-f]+:[   ]+9211600b[     ]+th.vmaqasu\.vv[       ]+v0,v2,v1
+[      ]+[0-9a-f]+:[   ]+9400600b[     ]+th.vmaqasu\.vx[       ]+v0,zero,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+9600600b[     ]+th.vmaqasu\.vx[       ]+v0,zero,v0
+[      ]+[0-9a-f]+:[   ]+9611600b[     ]+th.vmaqasu\.vx[       ]+v0,sp,v1
+[      ]+[0-9a-f]+:[   ]+9c00600b[     ]+th.vmaqaus\.vx[       ]+v0,zero,v0,v0\.t
+[      ]+[0-9a-f]+:[   ]+9e00600b[     ]+th.vmaqaus\.vx[       ]+v0,zero,v0
+[      ]+[0-9a-f]+:[   ]+9e11600b[     ]+th.vmaqaus\.vx[       ]+v0,sp,v1

diff --git a/gas/testsuite/gas/riscv/x-thead-vdot.s b/gas/testsuite/gas/riscv/x-thead-vdot.s
new file mode 100644 (file)
index 0000000..77c0546
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vdot.s
@@ -0,0 +1,31 @@
+
+.text
+
+test_int8_int4:
+       th.vmaqa.vv v0, v0, v0, v0.t
+       th.vmaqa.vv v0, v0, v0
+       th.vmaqa.vv v0, v2, v1
+
+       th.vmaqa.vx v0, x0, v0, v0.t
+       th.vmaqa.vx v0, x0, v0
+       th.vmaqa.vx v0, x2, v1
+
+       th.vmaqau.vv v0, v0, v0, v0.t
+       th.vmaqau.vv v0, v0, v0
+       th.vmaqau.vv v0, v2, v1
+
+       th.vmaqau.vx v0, x0, v0, v0.t
+       th.vmaqau.vx v0, x0, v0
+       th.vmaqau.vx v0, x2, v1
+
+       th.vmaqasu.vv v0, v0, v0, v0.t
+       th.vmaqasu.vv v0, v0, v0
+       th.vmaqasu.vv v0, v2, v1
+
+       th.vmaqasu.vx v0, x0, v0, v0.t
+       th.vmaqasu.vx v0, x0, v0
+       th.vmaqasu.vx v0, x2, v1
+
+       th.vmaqaus.vx v0, x0, v0, v0.t
+       th.vmaqaus.vx v0, x0, v0
+       th.vmaqaus.vx v0, x2, v1

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24af3ac531b78041d05f465b7cc00a824f7e32d4..1f56317e2550954c7fcfb3b50ef88022b659bc24 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3699,6 +3699,21 @@
 #define MASK_TH_VFMVFS 0xfe0ff07f
 #define MATCH_TH_VFMVSF 0x36005057
 #define MASK_TH_VFMVSF 0xfff0707f
+/* Vendor-specific (T-Head) XTheadVdot instructions.  */
+#define MATCH_TH_VMAQA_VV 0x8000600b
+#define MASK_TH_VMAQA_VV 0xfc00707f
+#define MATCH_TH_VMAQA_VX 0x8400600b
+#define MASK_TH_VMAQA_VX 0xfc00707f
+#define MATCH_TH_VMAQAU_VV 0x8800600b
+#define MASK_TH_VMAQAU_VV 0xfc00707f
+#define MATCH_TH_VMAQAU_VX 0x8c00600b
+#define MASK_TH_VMAQAU_VX 0xfc00707f
+#define MATCH_TH_VMAQASU_VV 0x9000600b
+#define MASK_TH_VMAQASU_VV 0xfc00707f
+#define MATCH_TH_VMAQASU_VX 0x9400600b
+#define MASK_TH_VMAQASU_VX 0xfc00707f
+#define MATCH_TH_VMAQAUS_VX 0x9c00600b
+#define MASK_TH_VMAQAUS_VX 0xfc00707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 6bcea638025c02fa76b59689a994aa93e5b73353..1f4bede428e67087a5c68d789aae9d6c0b6c0630 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -554,6 +554,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADMEMPAIR,
   INSN_CLASS_XTHEADSYNC,
   INSN_CLASS_XTHEADVECTOR,
+  INSN_CLASS_XTHEADVDOT,
   INSN_CLASS_XTHEADZVAMO,
   INSN_CLASS_XVENTANACONDOPS,
   INSN_CLASS_XSFVCP,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 9e6c2ae45fb78409cbc2e92f6690b0c750ebc698..b83dcabf7fc46ad823c172b83b6641d4de66ac27 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3459,6 +3459,15 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0},
 {"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0},
 
+/* Vendor-specific (T-Head) XTheadVdot instructions.  */
+{"th.vmaqa.vv",        0, INSN_CLASS_XTHEADVDOT,  "Vd,Vs,VtVm",  MATCH_TH_VMAQA_VV, MASK_TH_VMAQA_VV, match_opcode, 0},
+{"th.vmaqau.vv",       0, INSN_CLASS_XTHEADVDOT,  "Vd,Vs,VtVm",  MATCH_TH_VMAQAU_VV, MASK_TH_VMAQAU_VV, match_opcode, 0},
+{"th.vmaqasu.vv",      0, INSN_CLASS_XTHEADVDOT,  "Vd,Vs,VtVm",  MATCH_TH_VMAQASU_VV, MASK_TH_VMAQASU_VV, match_opcode, 0},
+{"th.vmaqa.vx",        0, INSN_CLASS_XTHEADVDOT,  "Vd,s,VtVm",  MATCH_TH_VMAQA_VX, MASK_TH_VMAQA_VX, match_opcode, 0},
+{"th.vmaqau.vx",       0, INSN_CLASS_XTHEADVDOT,  "Vd,s,VtVm",  MATCH_TH_VMAQAU_VX, MASK_TH_VMAQAU_VX, match_opcode, 0},
+{"th.vmaqasu.vx",      0, INSN_CLASS_XTHEADVDOT,  "Vd,s,VtVm",  MATCH_TH_VMAQASU_VX, MASK_TH_VMAQASU_VX, match_opcode, 0},
+{"th.vmaqaus.vx",      0, INSN_CLASS_XTHEADVDOT,  "Vd,s,VtVm",  MATCH_TH_VMAQAUS_VX, MASK_TH_VMAQAUS_VX, match_opcode, 0},
+
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
 {"vt.maskcn",  64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },