rs6000: Do not reorder operands for vec_pack_to_short_fp32 based on endianness

The patterns for altivec_vpku<VI_char>um take care of the order of
operands for the vpkuwum instruction, and therefore it is not needed in
the define_expand pattern "convert_4f32_8f16".

2025-11-18  Avinash Jayakar  <avinashd@linux.ibm.com>

gcc/ChangeLog:
	PR target/119130
	* config/rs6000/altivec.md (convert_4f32_8f16): Use same operand
	order for both endian format.

gcc/testsuite/ChangeLog:
	PR target/119130
	* gcc.target/powerpc/builtins-1-p9-runnable.c: Use same expected
	results for both endian format.

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index fa3368079ada661f3f159e27a3cf793698df1760..3336b0c75ddfb1e8b1dfb9501bb3ac473a8da71f 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -3625,10 +3625,7 @@
 
   emit_insn (gen_vsx_xvcvsphp (rtx_tmp_hi, operands[1]));
   emit_insn (gen_vsx_xvcvsphp (rtx_tmp_lo, operands[2]));
-  if (!BYTES_BIG_ENDIAN)
-    emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_hi, rtx_tmp_lo));
-  else
-    emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_lo, rtx_tmp_hi));
+  emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_hi, rtx_tmp_lo));
   DONE;
 })
 

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c
index 976654155b1a692e90fb29def2deb9e0bd8f2ee9..500db87d7e0138733cde4fa33fbaf87e22d5789b 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c
@@ -16,13 +16,8 @@ int main() {
   vfb = (vector float){10.0, -2.0, 70.0, 999.0 };
 
   /* Expected results.  */
-#ifdef __BIG_ENDIAN__
-  vexpected = (vector unsigned short) { 0x4900, 0xc000, 0x5460, 0x63ce,
-                                       0x3666, 0x3e66, 0x4d00, 0x563e };
-#else
   vexpected = (vector unsigned short) { 0x3666, 0x3e66, 0x4d00, 0x563e,
                                        0x4900, 0xc000, 0x5460, 0x63ce };
-#endif
 
 /*
      vresult = vec_pack_to_short_fp32 (vfa, vfb);