drm/xe: Save CTX_TIMESTAMP mmio value instead of LRC value

For determining actual job execution time, save the current value of the
CTX_TIMESTAMP register rather than the value saved in LRC since the
current register value is the closest to the start time of the job.

v2: Define MI_STORE_REGISTER_MEM to fix compile error
v3: Place MI_STORE_REGISTER_MEM sorted by MI_INSTR (Lucas)

Fixes: 65921374c48f ("drm/xe: Emit ctx timestamp copy in ring ops")
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20250509161159.2173069-6-umesh.nerlige.ramappa@intel.com
(cherry picked from commit 38b14233e5deff51db8faec287b4acd227152246)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
index 167fb0f742de7b15062989cf485ddeaf0a4db801..5a47991b4b81fc6f7263a0365fac166bb49981e4 100644 (file)
--- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
@@ -47,6 +47,10 @@
 #define   MI_LRI_FORCE_POSTED          REG_BIT(12)
 #define   MI_LRI_LEN(x)                        (((x) & 0xff) + 1)
 
+#define MI_STORE_REGISTER_MEM          (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))
+#define   MI_SRM_USE_GGTT              REG_BIT(22)
+#define   MI_SRM_ADD_CS_OFFSET         REG_BIT(19)
+
 #define MI_FLUSH_DW                    __MI_INSTR(0x26)
 #define   MI_FLUSH_DW_PROTECTED_MEM_EN REG_BIT(22)
 #define   MI_FLUSH_DW_STORE_INDEX      REG_BIT(21)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index df3ceddede070a82357e0537349027313b1b4ddb..48e8fd85eabe352bed6f4e23ecc33a210a6dee99 100644 (file)
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -684,7 +684,7 @@ static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)
 
 static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc)
 {
-       /* The start seqno is stored in the driver-defined portion of PPHWSP */
+       /* This is stored in the driver-defined portion of PPHWSP */
        return xe_lrc_pphwsp_offset(lrc) + LRC_CTX_JOB_TIMESTAMP_OFFSET;
 }
 

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index a7582b097ae678a00008d2be3d18ad4aca036311..bc1689db4cd7165d4a6c52db84af5c693c8a8001 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -234,13 +234,10 @@ static u32 get_ppgtt_flag(struct xe_sched_job *job)
 
 static int emit_copy_timestamp(struct xe_lrc *lrc, u32 *dw, int i)
 {
-       dw[i++] = MI_COPY_MEM_MEM | MI_COPY_MEM_MEM_SRC_GGTT |
-               MI_COPY_MEM_MEM_DST_GGTT;
+       dw[i++] = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET;
+       dw[i++] = RING_CTX_TIMESTAMP(0).addr;
        dw[i++] = xe_lrc_ctx_job_timestamp_ggtt_addr(lrc);
        dw[i++] = 0;
-       dw[i++] = xe_lrc_ctx_timestamp_ggtt_addr(lrc);
-       dw[i++] = 0;
-       dw[i++] = MI_NOOP;
 
        return i;
 }