net: stmmac: dwmac4: Receive Watchdog Timeout is not in abnormal interrupt summary

The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal
Interrupt Summary (AIS). Move the RWT handling out of the AIS
condition statement.

From databook, the AIS is the logical OR of the following interrupt bits:

- Bit 1: Transmit Process Stopped
- Bit 7: Receive Buffer Unavailable
- Bit 8: Receive Process Stopped
- Bit 10: Early Transmit Interrupt
- Bit 12: Fatal Bus Error
- Bit 13: Context Descriptor Error

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20241107063637.2122726-4-leyfoon.tan@starfivetech.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
index 0d185e54eb7e24cfd4ef8de38e976aabd3ee9084..57c03d491774475a963850c58c50e16972cbef6c 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
@@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
                        x->rx_buf_unav_irq++;
                if (unlikely(intr_status & DMA_CHAN_STATUS_RPS))
                        x->rx_process_stopped_irq++;
-               if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))
-                       x->rx_watchdog_irq++;
                if (unlikely(intr_status & DMA_CHAN_STATUS_ETI))
                        x->tx_early_irq++;
                if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) {
@@ -198,6 +196,10 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
                        ret = tx_hard_error;
                }
        }
+
+       if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))
+               x->rx_watchdog_irq++;
+
        /* TX/RX NORMAL interrupts */
        if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
                u64_stats_update_begin(&stats->syncp);