if (ret)
goto err_disable_clks;
- value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
- & priv->hw->mii.clk_csr_mask;
- value |= MII_XGMAC_READ;
+ value |= priv->gmii_address_bus_config | MII_XGMAC_READ;
/* Wait until any existing MII operation is complete */
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
if (ret)
goto err_disable_clks;
- value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
- & priv->hw->mii.clk_csr_mask;
- value |= phydata;
- value |= MII_XGMAC_WRITE;
+ value |= priv->gmii_address_bus_config | phydata | MII_XGMAC_WRITE;
/* Wait until any existing MII operation is complete */
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
return ((pa << mii_regs->addr_shift) & mii_regs->addr_mask) |
((gr << mii_regs->reg_shift) & mii_regs->reg_mask) |
- ((priv->clk_csr << mii_regs->clk_csr_shift) &
- mii_regs->clk_csr_mask) |
+ priv->gmii_address_bus_config |
MII_BUSY;
}
priv->hw->xpcs = NULL;
}
+static void stmmac_mdio_bus_config(struct stmmac_priv *priv, u32 value)
+{
+ value <<= priv->hw->mii.clk_csr_shift;
+
+ if (value & ~priv->hw->mii.clk_csr_mask)
+ dev_warn(priv->device,
+ "clk_csr value out of range (0x%08x exceeds mask 0x%08x), truncating\n",
+ value, priv->hw->mii.clk_csr_mask);
+
+ priv->gmii_address_bus_config = value & priv->hw->mii.clk_csr_mask;
+}
+
/**
* stmmac_mdio_register
* @ndev: net device structure
if (!mdio_bus_data)
return 0;
+ stmmac_mdio_bus_config(priv, priv->clk_csr);
+
new_bus = mdiobus_alloc();
if (!new_bus)
return -ENOMEM;