drm/i915/dsb: Document that the ATS fault bits are for mtl+

The ATS faults have something to do with some new iommu stuff
on mtl+. Document that the relevant DSB interrupt bits aren't
valid for earlier platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-11-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
index 210e2665441d5ddab821c94b10dc8c85c8458674..9c2664ff519aee5ef032c0ba52b36650ed60430f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
@@ -51,12 +51,12 @@
 #define   DSB_RESET_SM_STATE_MASK      REG_GENMASK(5, 4)
 #define   DSB_RUN_SM_STATE_MASK                REG_GENMASK(2, 0)
 #define DSB_INTERRUPT(pipe, id)                _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
-#define   DSB_ATS_FAULT_INT_EN         REG_BIT(20)
+#define   DSB_ATS_FAULT_INT_EN         REG_BIT(20) /* mtl+ */
 #define   DSB_GTT_FAULT_INT_EN         REG_BIT(19)
 #define   DSB_RSPTIMEOUT_INT_EN                REG_BIT(18)
 #define   DSB_POLL_ERR_INT_EN          REG_BIT(17)
 #define   DSB_PROG_INT_EN              REG_BIT(16)
-#define   DSB_ATS_FAULT_INT_STATUS     REG_BIT(4)
+#define   DSB_ATS_FAULT_INT_STATUS     REG_BIT(4) /* mtl+ */
 #define   DSB_GTT_FAULT_INT_STATUS     REG_BIT(3)
 #define   DSB_RSPTIMEOUT_INT_STATUS    REG_BIT(2)
 #define   DSB_POLL_ERR_INT_STATUS      REG_BIT(1)