]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915: ARL requires a newer GSC firmware
authorJohn Harrison <John.C.Harrison@Intel.com>
Fri, 2 Aug 2024 03:10:51 +0000 (20:10 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Mon, 26 Aug 2024 14:21:11 +0000 (10:21 -0400)
ARL and MTL share a single GSC firmware blob. However, ARL requires a
newer version of it.

So add differentiate of the PCI ids for ARL from MTL and create ARL as
a sub-platform of MTL. That way, all the existing workarounds and such
still treat ARL as MTL exactly as before. However, now the GSC code
can check for ARL and do an extra version check on the firmware before
committing to it.

Also, the version extraction code has various ways of failing but the
return code was being ignore and so the firmware load would attempt to
continue anyway. Fix that by propagating the return code to the next
level out.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Fixes: 213c43676beb ("drm/i915/mtl: Remove the 'force_probe' requirement for Meteor Lake")
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240802031051.3816392-1-John.C.Harrison@Intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h
include/drm/intel/i915_pciids.h

index 3b69bc6616bd34f042e69c4c77767a9e9f454e0d..551b0d7974ff13fcdc03a1c809f8c5dfbe146fa4 100644 (file)
@@ -212,6 +212,37 @@ int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data, s
                }
        }
 
+       if (IS_ARROWLAKE(gt->i915)) {
+               bool too_old = false;
+
+               /*
+                * ARL requires a newer firmware than MTL did (102.0.10.1878) but the
+                * firmware is actually common. So, need to do an explicit version check
+                * here rather than using a separate table entry. And if the older
+                * MTL-only version is found, then just don't use GSC rather than aborting
+                * the driver load.
+                */
+               if (gsc->release.major < 102) {
+                       too_old = true;
+               } else if (gsc->release.major == 102) {
+                       if (gsc->release.minor == 0) {
+                               if (gsc->release.patch < 10) {
+                                       too_old = true;
+                               } else if (gsc->release.patch == 10) {
+                                       if (gsc->release.build < 1878)
+                                               too_old = true;
+                               }
+                       }
+               }
+
+               if (too_old) {
+                       gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least 102.0.10.1878",
+                               gsc->release.major, gsc->release.minor,
+                               gsc->release.patch, gsc->release.build);
+                       return -EINVAL;
+               }
+       }
+
        return 0;
 }
 
index d80278eb45d734e90703341e00c77ea529420d5b..ec33ad942115abd980f6ee83f2f9080165c81a13 100644 (file)
@@ -698,12 +698,18 @@ static int check_gsc_manifest(struct intel_gt *gt,
                              const struct firmware *fw,
                              struct intel_uc_fw *uc_fw)
 {
+       int ret;
+
        switch (uc_fw->type) {
        case INTEL_UC_FW_TYPE_HUC:
-               intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size);
+               ret = intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size);
+               if (ret)
+                       return ret;
                break;
        case INTEL_UC_FW_TYPE_GSC:
-               intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size);
+               ret = intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size);
+               if (ret)
+                       return ret;
                break;
        default:
                MISSING_CASE(uc_fw->type);
index eb4c33e83c7c0af69a96c5428a52b92b18632ac3..d772cbe15fec12ab073a431a5b97fd8b1ee58fa9 100644 (file)
@@ -536,6 +536,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_LUNARLAKE(i915) (0 && i915)
 #define IS_BATTLEMAGE(i915)  (0 && i915)
 
+#define IS_ARROWLAKE(i915) \
+       IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
 #define IS_DG2_G10(i915) \
        IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(i915) \
index b485e959f064a61fee09c7c2088817279af885c8..3c47c625993e421e370fd0c8f83ea62be0547638 100644 (file)
@@ -200,6 +200,10 @@ static const u16 subplatform_g12_ids[] = {
        INTEL_DG2_G12_IDS(ID),
 };
 
+static const u16 subplatform_arl_ids[] = {
+       INTEL_ARL_IDS(ID),
+};
+
 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 {
        for (; num; num--, p++) {
@@ -257,6 +261,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
        } else if (find_devid(devid, subplatform_g12_ids,
                              ARRAY_SIZE(subplatform_g12_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_G12);
+       } else if (find_devid(devid, subplatform_arl_ids,
+                             ARRAY_SIZE(subplatform_arl_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_ARL);
        }
 
        GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
index fb8a08623eb01720ee7dee141def2aba96ea8049..643ff1bf74eeb0d14b4c18fc33f75d22bd35a87c 100644 (file)
@@ -127,6 +127,9 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_N    1
 #define INTEL_SUBPLATFORM_RPLU  2
 
+/* MTL */
+#define INTEL_SUBPLATFORM_ARL  0
+
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
index b21374f76df2387dd537f8c5521496ebafdcd13a..2bf03ebfcf73da80a4f35f8ebf79fe5b83b9e1d9 100644 (file)
        INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
 
 /* MTL */
+#define INTEL_ARL_IDS(MACRO__, ...) \
+       MACRO__(0x7D41, ## __VA_ARGS__), \
+       MACRO__(0x7D51, ## __VA_ARGS__), \
+       MACRO__(0x7D67, ## __VA_ARGS__), \
+       MACRO__(0x7DD1, ## __VA_ARGS__)
+
 #define INTEL_MTL_IDS(MACRO__, ...) \
+       INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
        MACRO__(0x7D40, ## __VA_ARGS__), \
-       MACRO__(0x7D41, ## __VA_ARGS__), \
        MACRO__(0x7D45, ## __VA_ARGS__), \
-       MACRO__(0x7D51, ## __VA_ARGS__), \
        MACRO__(0x7D55, ## __VA_ARGS__), \
        MACRO__(0x7D60, ## __VA_ARGS__), \
-       MACRO__(0x7D67, ## __VA_ARGS__), \
-       MACRO__(0x7DD1, ## __VA_ARGS__), \
        MACRO__(0x7DD5, ## __VA_ARGS__)
 
 /* LNL */