--- /dev/null
+From d1585c89cecdb513f68045e47ab76976524b5961 Mon Sep 17 00:00:00 2001
+From: Libin Yang <libin.yang@intel.com>
+Date: Mon, 4 Aug 2014 09:22:45 +0800
+Subject: ALSA: hda - add codec ID for Braswell display audio codec
+
+From: Libin Yang <libin.yang@intel.com>
+
+commit d1585c89cecdb513f68045e47ab76976524b5961 upstream.
+
+This patch adds codec ID (0x80862883) and module alias for Braswell
+display codec.
+
+Signed-off-by: Libin Yang <libin.yang@intel.com>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/pci/hda/patch_hdmi.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/sound/pci/hda/patch_hdmi.c
++++ b/sound/pci/hda/patch_hdmi.c
+@@ -3317,6 +3317,7 @@ static const struct hda_codec_preset snd
+ { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
+ { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
+ { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
++{ .id = 0x80862883, .name = "Braswell HDMI", .patch = patch_generic_hdmi },
+ { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
+ {} /* terminator */
+ };
+@@ -3373,6 +3374,7 @@ MODULE_ALIAS("snd-hda-codec-id:80862807"
+ MODULE_ALIAS("snd-hda-codec-id:80862808");
+ MODULE_ALIAS("snd-hda-codec-id:80862880");
+ MODULE_ALIAS("snd-hda-codec-id:80862882");
++MODULE_ALIAS("snd-hda-codec-id:80862883");
+ MODULE_ALIAS("snd-hda-codec-id:808629fb");
+
+ MODULE_LICENSE("GPL");
--- /dev/null
+From f31b2ffcad2b8c57cee5ffc634928bcbc8c6a558 Mon Sep 17 00:00:00 2001
+From: Libin Yang <libin.yang@intel.com>
+Date: Mon, 4 Aug 2014 09:22:44 +0800
+Subject: ALSA: hda - add PCI IDs for Intel Braswell
+
+From: Libin Yang <libin.yang@intel.com>
+
+commit f31b2ffcad2b8c57cee5ffc634928bcbc8c6a558 upstream.
+
+Add HD Audio Device PCI ID for the Intel Braswell platform.
+It is an HDA Intel PCH controller.
+
+AZX_DCAPS_ALIGN_BUFSIZE is not necessary for this controller.
+
+Signed-off-by: Libin Yang <libin.yang@intel.com>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/pci/hda/hda_intel.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/sound/pci/hda/hda_intel.c
++++ b/sound/pci/hda/hda_intel.c
+@@ -4027,6 +4027,9 @@ static DEFINE_PCI_DEVICE_TABLE(azx_ids)
+ /* BayTrail */
+ { PCI_DEVICE(0x8086, 0x0f04),
+ .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
++ /* Braswell */
++ { PCI_DEVICE(0x8086, 0x2284),
++ .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
+ /* ICH */
+ { PCI_DEVICE(0x8086, 0x2668),
+ .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
--- /dev/null
+From c034b02e213d271b98c45c4a7b54af8f69aaac1e Mon Sep 17 00:00:00 2001
+From: Dirk Brandewie <dirk.j.brandewie@intel.com>
+Date: Mon, 13 Oct 2014 08:37:40 -0700
+Subject: cpufreq: expose scaling_cur_freq sysfs file for set_policy() drivers
+
+From: Dirk Brandewie <dirk.j.brandewie@intel.com>
+
+commit c034b02e213d271b98c45c4a7b54af8f69aaac1e upstream.
+
+Currently the core does not expose scaling_cur_freq for set_policy()
+drivers this breaks some userspace monitoring tools.
+Change the core to expose this file for all drivers and if the
+set_policy() driver supports the get() callback use it to retrieve the
+current frequency.
+
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=73741
+Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/cpufreq/cpufreq.c | 23 +++++++++++++++++------
+ 1 file changed, 17 insertions(+), 6 deletions(-)
+
+--- a/drivers/cpufreq/cpufreq.c
++++ b/drivers/cpufreq/cpufreq.c
+@@ -460,7 +460,18 @@ show_one(cpuinfo_max_freq, cpuinfo.max_f
+ show_one(cpuinfo_transition_latency, cpuinfo.transition_latency);
+ show_one(scaling_min_freq, min);
+ show_one(scaling_max_freq, max);
+-show_one(scaling_cur_freq, cur);
++
++static ssize_t show_scaling_cur_freq(
++ struct cpufreq_policy *policy, char *buf)
++{
++ ssize_t ret;
++
++ if (cpufreq_driver && cpufreq_driver->setpolicy && cpufreq_driver->get)
++ ret = sprintf(buf, "%u\n", cpufreq_driver->get(policy->cpu));
++ else
++ ret = sprintf(buf, "%u\n", policy->cur);
++ return ret;
++}
+
+ static int cpufreq_set_policy(struct cpufreq_policy *policy,
+ struct cpufreq_policy *new_policy);
+@@ -854,11 +865,11 @@ static int cpufreq_add_dev_interface(str
+ if (ret)
+ goto err_out_kobj_put;
+ }
+- if (has_target()) {
+- ret = sysfs_create_file(&policy->kobj, &scaling_cur_freq.attr);
+- if (ret)
+- goto err_out_kobj_put;
+- }
++
++ ret = sysfs_create_file(&policy->kobj, &scaling_cur_freq.attr);
++ if (ret)
++ goto err_out_kobj_put;
++
+ if (cpufreq_driver->bios_limit) {
+ ret = sysfs_create_file(&policy->kobj, &bios_limit.attr);
+ if (ret)
--- /dev/null
+From 16405f98bca8eb39a23b3ce03e241ca19e7af370 Mon Sep 17 00:00:00 2001
+From: Mika Westerberg <mika.westerberg@linux.intel.com>
+Date: Fri, 22 Aug 2014 13:05:44 +0300
+Subject: cpufreq: intel_pstate: Add CPU ID for Braswell processor
+
+From: Mika Westerberg <mika.westerberg@linux.intel.com>
+
+commit 16405f98bca8eb39a23b3ce03e241ca19e7af370 upstream.
+
+This is pretty much the same as Intel Baytrail, only the CPU ID is
+different. Add the new ID to the supported CPU list.
+
+Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Acked-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/cpufreq/intel_pstate.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/cpufreq/intel_pstate.c
++++ b/drivers/cpufreq/intel_pstate.c
+@@ -690,6 +690,7 @@ static const struct x86_cpu_id intel_pst
+ ICPU(0x3f, core_params),
+ ICPU(0x45, core_params),
+ ICPU(0x46, core_params),
++ ICPU(0x4c, byt_params),
+ ICPU(0x4f, core_params),
+ ICPU(0x56, core_params),
+ {}
--- /dev/null
+From 36b4bed5cd8f6e17019fa7d380e0836872c7b367 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali.rohar@gmail.com>
+Date: Thu, 16 Oct 2014 01:16:51 +0200
+Subject: cpufreq: intel_pstate: Fix setting max_perf_pct in performance policy
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali.rohar@gmail.com>
+
+commit 36b4bed5cd8f6e17019fa7d380e0836872c7b367 upstream.
+
+Code which changes policy to powersave changes also max_policy_pct based on
+max_freq. Code which change max_perf_pct has upper limit base on value
+max_policy_pct. When policy is changing from powersave back to performance
+then max_policy_pct is not changed. Which means that changing max_perf_pct is
+not possible to high values if max_freq was too low in powersave policy.
+
+Test case:
+
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
+800000
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
+3300000
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
+performance
+$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
+100
+
+$ echo powersave > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
+$ echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
+$ echo 20 > /sys/devices/system/cpu/intel_pstate/max_perf_pct
+
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
+powersave
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
+800000
+$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
+20
+
+$ echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
+$ echo 3300000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
+$ echo 100 > /sys/devices/system/cpu/intel_pstate/max_perf_pct
+
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
+performance
+$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
+3300000
+$ cat /sys/devices/system/cpu/intel_pstate/max_perf_pct
+24
+
+And now intel_pstate driver allows to set maximal value for max_perf_pct based
+on max_policy_pct which is 24 for previous powersave max_freq 800000.
+
+This patch will set default value for max_policy_pct when setting policy to
+performance so it will allow to set also max value for max_perf_pct.
+
+Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
+Acked-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/cpufreq/intel_pstate.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/cpufreq/intel_pstate.c
++++ b/drivers/cpufreq/intel_pstate.c
+@@ -751,6 +751,7 @@ static int intel_pstate_set_policy(struc
+ if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
+ limits.min_perf_pct = 100;
+ limits.min_perf = int_tofp(1);
++ limits.max_policy_pct = 100;
+ limits.max_perf_pct = 100;
+ limits.max_perf = int_tofp(1);
+ limits.no_turbo = limits.turbo_disabled;
--- /dev/null
+From c7e241df5970171e3e86a516f91ca8a30ca516e8 Mon Sep 17 00:00:00 2001
+From: Dirk Brandewie <dirk.j.brandewie@intel.com>
+Date: Thu, 8 May 2014 12:57:27 -0700
+Subject: intel_pstate: Add CPU IDs for Broadwell processors
+
+From: Dirk Brandewie <dirk.j.brandewie@intel.com>
+
+commit c7e241df5970171e3e86a516f91ca8a30ca516e8 upstream.
+
+Add support for Broadwell processors.
+
+Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/cpufreq/intel_pstate.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/cpufreq/intel_pstate.c
++++ b/drivers/cpufreq/intel_pstate.c
+@@ -685,10 +685,13 @@ static const struct x86_cpu_id intel_pst
+ ICPU(0x37, byt_params),
+ ICPU(0x3a, core_params),
+ ICPU(0x3c, core_params),
++ ICPU(0x3d, core_params),
+ ICPU(0x3e, core_params),
+ ICPU(0x3f, core_params),
+ ICPU(0x45, core_params),
+ ICPU(0x46, core_params),
++ ICPU(0x4f, core_params),
++ ICPU(0x56, core_params),
+ {}
+ };
+ MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
--- /dev/null
+From 43e968cec79b6334cf7cb3e11184cce720541712 Mon Sep 17 00:00:00 2001
+From: Derek Browne <Derek.Browne@intel.com>
+Date: Tue, 24 Jun 2014 06:56:36 -0700
+Subject: mmc: sdhci-pci: SDIO host controller support for Intel Quark X1000
+
+From: Derek Browne <Derek.Browne@intel.com>
+
+commit 43e968cec79b6334cf7cb3e11184cce720541712 upstream.
+
+This patch is to enable SDIO host controller for Intel Quark X1000.
+
+Signed-off-by: Derek Browne <Derek.Browne@intel.com>
+Signed-off-by: Alvin (Weike) Chen <alvin.chen@intel.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/host/sdhci-pci.c | 12 ++++++++++++
+ drivers/mmc/host/sdhci-pci.h | 1 +
+ 2 files changed, 13 insertions(+)
+
+--- a/drivers/mmc/host/sdhci-pci.c
++++ b/drivers/mmc/host/sdhci-pci.c
+@@ -103,6 +103,10 @@ static const struct sdhci_pci_fixes sdhc
+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ };
+
++static const struct sdhci_pci_fixes sdhci_intel_qrk = {
++ .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
++};
++
+ static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
+ {
+ slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+@@ -732,6 +736,14 @@ static const struct pci_device_id pci_id
+ },
+
+ {
++ .vendor = PCI_VENDOR_ID_INTEL,
++ .device = PCI_DEVICE_ID_INTEL_QRK_SD,
++ .subvendor = PCI_ANY_ID,
++ .subdevice = PCI_ANY_ID,
++ .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
++ },
++
++ {
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
+ .subvendor = PCI_ANY_ID,
+--- a/drivers/mmc/host/sdhci-pci.h
++++ b/drivers/mmc/host/sdhci-pci.h
+@@ -17,6 +17,7 @@
+ #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
+ #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
+ #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
++#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
+
+ /*
+ * PCI registers
ext4-fix-overflow-when-updating-superblock-backups-after-resize.patch
ext4-enable-journal-checksum-when-metadata-checksum-feature-enabled.patch
ext4-fix-oops-when-loading-block-bitmap-failed.patch
+cpufreq-expose-scaling_cur_freq-sysfs-file-for-set_policy-drivers.patch
+cpufreq-intel_pstate-fix-setting-max_perf_pct-in-performance-policy.patch
+intel_pstate-add-cpu-ids-for-broadwell-processors.patch
+cpufreq-intel_pstate-add-cpu-id-for-braswell-processor.patch
+x86-iosf-make-iosf-driver-modular-and-usable-by-more-drivers.patch
+x86-iosf-added-quark-mbi-identifiers.patch
+x86-iosf-add-quark-x1000-pci-id.patch
+x86-iosf-add-pci-id-macros-for-better-readability.patch
+x86-add-cpu_detect_cache_sizes-to-init_intel-add-quark-legacy_cache.patch
+mmc-sdhci-pci-sdio-host-controller-support-for-intel-quark.patch
+x86-platform-intel-iosf-add-braswell-pci-id.patch
+alsa-hda-add-pci-ids-for-intel-braswell.patch
+alsa-hda-add-codec-id-for-braswell-display-audio-codec.patch
--- /dev/null
+From aece118e487a744eafcdd0c77fe32b55ee2092a1 Mon Sep 17 00:00:00 2001
+From: Bryan O'Donoghue <pure.logic@nexus-software.ie>
+Date: Tue, 7 Oct 2014 01:19:49 +0100
+Subject: x86: Add cpu_detect_cache_sizes to init_intel() add Quark legacy_cache()
+
+From: Bryan O'Donoghue <pure.logic@nexus-software.ie>
+
+commit aece118e487a744eafcdd0c77fe32b55ee2092a1 upstream.
+
+Intel processors which don't report cache information via cpuid(2)
+or cpuid(4) need quirk code in the legacy_cache_size callback to
+report this data. For Intel that callback is is intel_size_cache().
+
+This patch enables calling of cpu_detect_cache_sizes() inside of
+init_intel() and hence the calling of the legacy_cache callback in
+intel_size_cache(). Adding this call will ensure that PIII Tualatin
+currently in intel_size_cache() and Quark SoC X1000 being added to
+intel_size_cache() in this patch will report their respective cache
+sizes.
+
+This model of calling cpu_detect_cache_sizes() is consistent with
+AMD/Via/Cirix/Transmeta and Centaur.
+
+Also added is a string to idenitfy the Quark as Quark SoC X1000
+giving better and more descriptive output via /proc/cpuinfo
+
+Adding cpu_detect_cache_sizes to init_intel() will enable calling
+of intel_size_cache() on Intel processors which currently no code
+can reach. Therefore this patch will also re-enable reporting
+of PIII Tualatin cache size information as well as add
+Quark SoC X1000 support.
+
+Comment text and cache flow logic suggested by Thomas Gleixner
+
+Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
+Cc: davej@redhat.com
+Cc: hmh@hmh.eng.br
+Link: http://lkml.kernel.org/r/1412641189-12415-3-git-send-email-pure.logic@nexus-software.ie
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/cpu/intel.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/arch/x86/kernel/cpu/intel.c
++++ b/arch/x86/kernel/cpu/intel.c
+@@ -383,6 +383,13 @@ static void init_intel(struct cpuinfo_x8
+ detect_extended_topology(c);
+
+ l2 = init_intel_cacheinfo(c);
++
++ /* Detect legacy cache sizes if init_intel_cacheinfo did not */
++ if (l2 == 0) {
++ cpu_detect_cache_sizes(c);
++ l2 = c->x86_cache_size;
++ }
++
+ if (c->cpuid_level > 9) {
+ unsigned eax = cpuid_eax(10);
+ /* Check for version and the number of counters */
+@@ -497,6 +504,13 @@ static unsigned int intel_size_cache(str
+ */
+ if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
+ size = 256;
++
++ /*
++ * Intel Quark SoC X1000 contains a 4-way set associative
++ * 16K cache with a 16 byte cache line and 256 lines per tag
++ */
++ if ((c->x86 == 5) && (c->x86_model == 9))
++ size = 16;
+ return size;
+ }
+ #endif
+@@ -724,7 +738,8 @@ static const struct cpu_dev intel_cpu_de
+ [3] = "OverDrive PODP5V83",
+ [4] = "Pentium MMX",
+ [7] = "Mobile Pentium 75 - 200",
+- [8] = "Mobile Pentium MMX"
++ [8] = "Mobile Pentium MMX",
++ [9] = "Quark SoC X1000",
+ }
+ },
+ { .family = 6, .model_names =
--- /dev/null
+From 04725ad59474d24553d526fa774179ecd2922342 Mon Sep 17 00:00:00 2001
+From: Ong Boon Leong <boon.leong.ong@intel.com>
+Date: Fri, 9 May 2014 13:44:08 -0700
+Subject: x86, iosf: Add PCI ID macros for better readability
+
+From: Ong Boon Leong <boon.leong.ong@intel.com>
+
+commit 04725ad59474d24553d526fa774179ecd2922342 upstream.
+
+Introduce PCI IDs macro for the list of supported product:
+BayTrail & Quark X1000.
+
+Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
+Link: http://lkml.kernel.org/r/1399668248-24199-5-git-send-email-david.e.box@linux.intel.com
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/iosf_mbi.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/iosf_mbi.c
++++ b/arch/x86/kernel/iosf_mbi.c
+@@ -25,6 +25,9 @@
+
+ #include <asm/iosf_mbi.h>
+
++#define PCI_DEVICE_ID_BAYTRAIL 0x0F00
++#define PCI_DEVICE_ID_QUARK_X1000 0x0958
++
+ static DEFINE_SPINLOCK(iosf_mbi_lock);
+
+ static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
+@@ -200,8 +203,8 @@ static int iosf_mbi_probe(struct pci_dev
+ }
+
+ static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
+- { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0F00) },
+- { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0958) },
++ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
++ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
+ { 0, },
+ };
+ MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
--- /dev/null
+From 90916e048c1e0c1d379577e43ab9b8e331490cfb Mon Sep 17 00:00:00 2001
+From: Ong Boon Leong <boon.leong.ong@intel.com>
+Date: Fri, 9 May 2014 13:44:07 -0700
+Subject: x86, iosf: Add Quark X1000 PCI ID
+
+From: Ong Boon Leong <boon.leong.ong@intel.com>
+
+commit 90916e048c1e0c1d379577e43ab9b8e331490cfb upstream.
+
+Add PCI device ID, i.e. that of the Host Bridge,
+for IOSF MBI driver.
+
+Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
+Link: http://lkml.kernel.org/r/1399668248-24199-4-git-send-email-david.e.box@linux.intel.com
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/iosf_mbi.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/x86/kernel/iosf_mbi.c
++++ b/arch/x86/kernel/iosf_mbi.c
+@@ -201,6 +201,7 @@ static int iosf_mbi_probe(struct pci_dev
+
+ static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0F00) },
++ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0958) },
+ { 0, },
+ };
+ MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
--- /dev/null
+From 7ef1def800e907edd28ddb1a5c64bae6b8749cdd Mon Sep 17 00:00:00 2001
+From: Ong Boon Leong <boon.leong.ong@intel.com>
+Date: Fri, 9 May 2014 13:44:06 -0700
+Subject: x86, iosf: Added Quark MBI identifiers
+
+From: Ong Boon Leong <boon.leong.ong@intel.com>
+
+commit 7ef1def800e907edd28ddb1a5c64bae6b8749cdd upstream.
+
+Added all the MBI units below and their associated read/write
+opcodes:
+ - Host Bridge Arbiter
+ - Host Bridge
+ - Remote Management Unit
+ - Memory Manager & eSRAM
+ - SoC Unit
+
+Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
+Link: http://lkml.kernel.org/r/1399668248-24199-3-git-send-email-david.e.box@linux.intel.com
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/include/asm/iosf_mbi.h | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/x86/include/asm/iosf_mbi.h
++++ b/arch/x86/include/asm/iosf_mbi.h
+@@ -50,6 +50,28 @@
+ #define BT_MBI_PCIE_READ 0x00
+ #define BT_MBI_PCIE_WRITE 0x01
+
++/* Quark available units */
++#define QRK_MBI_UNIT_HBA 0x00
++#define QRK_MBI_UNIT_HB 0x03
++#define QRK_MBI_UNIT_RMU 0x04
++#define QRK_MBI_UNIT_MM 0x05
++#define QRK_MBI_UNIT_MMESRAM 0x05
++#define QRK_MBI_UNIT_SOC 0x31
++
++/* Quark read/write opcodes */
++#define QRK_MBI_HBA_READ 0x10
++#define QRK_MBI_HBA_WRITE 0x11
++#define QRK_MBI_HB_READ 0x10
++#define QRK_MBI_HB_WRITE 0x11
++#define QRK_MBI_RMU_READ 0x10
++#define QRK_MBI_RMU_WRITE 0x11
++#define QRK_MBI_MM_READ 0x10
++#define QRK_MBI_MM_WRITE 0x11
++#define QRK_MBI_MMESRAM_READ 0x12
++#define QRK_MBI_MMESRAM_WRITE 0x13
++#define QRK_MBI_SOC_READ 0x06
++#define QRK_MBI_SOC_WRITE 0x07
++
+ #if IS_ENABLED(CONFIG_IOSF_MBI)
+
+ bool iosf_mbi_available(void);
--- /dev/null
+From 6b8f0c8780c71d78624f736d7849645b64cc88b7 Mon Sep 17 00:00:00 2001
+From: "David E. Box" <david.e.box@linux.intel.com>
+Date: Fri, 9 May 2014 13:44:05 -0700
+Subject: x86, iosf: Make IOSF driver modular and usable by more drivers
+
+From: "David E. Box" <david.e.box@linux.intel.com>
+
+commit 6b8f0c8780c71d78624f736d7849645b64cc88b7 upstream.
+
+Currently drivers that run on non-IOSF systems (Core/Xeon) can't use the IOSF
+driver on SOC's without selecting it which forces an unnecessary and limiting
+dependency. Provides dummy functions to allow these modules to conditionally
+use the driver on IOSF equipped platforms without impacting their ability to
+compile and load on non-IOSF platforms. Build default m to ensure availability
+on x86 SOC's.
+
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Link: http://lkml.kernel.org/r/1399668248-24199-2-git-send-email-david.e.box@linux.intel.com
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/Kconfig | 7 ++-----
+ arch/x86/include/asm/iosf_mbi.h | 33 +++++++++++++++++++++++++++++++++
+ arch/x86/kernel/iosf_mbi.c | 7 +++++++
+ 3 files changed, 42 insertions(+), 5 deletions(-)
+
+--- a/arch/x86/Kconfig
++++ b/arch/x86/Kconfig
+@@ -2436,12 +2436,9 @@ config X86_DMA_REMAP
+ depends on STA2X11
+
+ config IOSF_MBI
+- bool
++ tristate
++ default m
+ depends on PCI
+- ---help---
+- To be selected by modules requiring access to the Intel OnChip System
+- Fabric (IOSF) Sideband MailBox Interface (MBI). For MBI platforms
+- enumerable by PCI.
+
+ source "net/Kconfig"
+
+--- a/arch/x86/include/asm/iosf_mbi.h
++++ b/arch/x86/include/asm/iosf_mbi.h
+@@ -50,6 +50,10 @@
+ #define BT_MBI_PCIE_READ 0x00
+ #define BT_MBI_PCIE_WRITE 0x01
+
++#if IS_ENABLED(CONFIG_IOSF_MBI)
++
++bool iosf_mbi_available(void);
++
+ /**
+ * iosf_mbi_read() - MailBox Interface read command
+ * @port: port indicating subunit being accessed
+@@ -87,4 +91,33 @@ int iosf_mbi_write(u8 port, u8 opcode, u
+ */
+ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
+
++#else /* CONFIG_IOSF_MBI is not enabled */
++static inline
++bool iosf_mbi_available(void)
++{
++ return false;
++}
++
++static inline
++int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
++{
++ WARN(1, "IOSF_MBI driver not available");
++ return -EPERM;
++}
++
++static inline
++int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
++{
++ WARN(1, "IOSF_MBI driver not available");
++ return -EPERM;
++}
++
++static inline
++int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
++{
++ WARN(1, "IOSF_MBI driver not available");
++ return -EPERM;
++}
++#endif /* CONFIG_IOSF_MBI */
++
+ #endif /* IOSF_MBI_SYMS_H */
+--- a/arch/x86/kernel/iosf_mbi.c
++++ b/arch/x86/kernel/iosf_mbi.c
+@@ -177,6 +177,13 @@ int iosf_mbi_modify(u8 port, u8 opcode,
+ }
+ EXPORT_SYMBOL(iosf_mbi_modify);
+
++bool iosf_mbi_available(void)
++{
++ /* Mbi isn't hot-pluggable. No remove routine is provided */
++ return mbi_pdev;
++}
++EXPORT_SYMBOL(iosf_mbi_available);
++
+ static int iosf_mbi_probe(struct pci_dev *pdev,
+ const struct pci_device_id *unused)
+ {
--- /dev/null
+From 849f5d894383d25c49132437aa289c9a9c98d5df Mon Sep 17 00:00:00 2001
+From: "David E. Box" <david.e.box@linux.intel.com>
+Date: Wed, 17 Sep 2014 22:13:49 -0700
+Subject: x86/platform/intel/iosf: Add Braswell PCI ID
+
+From: "David E. Box" <david.e.box@linux.intel.com>
+
+commit 849f5d894383d25c49132437aa289c9a9c98d5df upstream.
+
+Add Braswell PCI ID to list of supported ID's for the IOSF driver.
+
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Link: http://lkml.kernel.org/r/1411017231-20807-2-git-send-email-david.e.box@linux.intel.com
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/iosf_mbi.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/x86/kernel/iosf_mbi.c
++++ b/arch/x86/kernel/iosf_mbi.c
+@@ -26,6 +26,7 @@
+ #include <asm/iosf_mbi.h>
+
+ #define PCI_DEVICE_ID_BAYTRAIL 0x0F00
++#define PCI_DEVICE_ID_BRASWELL 0x2280
+ #define PCI_DEVICE_ID_QUARK_X1000 0x0958
+
+ static DEFINE_SPINLOCK(iosf_mbi_lock);
+@@ -204,6 +205,7 @@ static int iosf_mbi_probe(struct pci_dev
+
+ static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
++ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
+ { 0, },
+ };
projects / thirdparty / kernel / stable-queue.git / commitdiff
