Revert "drm/i915/psr: Implement WA to help reach PC10"

This reverts commit c2579a217799ba577fa39a2a12643a277334e691.

Reverting this commit as it is suspected being culprit on regression.

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240930071329.1630583-1-jouni.hogander@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7fb3eeb0e0f291dcbadc53c7640ae9575a971fb1..17fc21f6ae362d6dac8d8fbd99ace4eb5f9d6d97 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1576,9 +1576,6 @@ struct intel_psr {
 #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE    0x40
 
        u32 debug;
-       bool is_dpkgc_configured;
-       bool is_dc5_entry_possible;
-       bool is_wa_delayed_vblank_limit;
        bool sink_support;
        bool source_support;
        bool enabled;

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 39aa46de15e431c8017002ed2dfe21d6c8eccd1c..e3357f3b5c705f5c457cc8cbe546af50d63ba629 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,7 +26,6 @@
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_damage_helper.h>
 #include <drm/drm_debugfs.h>
-#include <drm/drm_vblank.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"
@@ -897,89 +896,6 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
        return idle_frames;
 }
 
-static bool
-intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
-{
-       return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
-}
-
-/*
- * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
- * VRR is not enabled
- */
-static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
-                                         struct intel_atomic_state *state)
-{
-       struct intel_crtc *intel_crtc;
-       struct intel_crtc_state *crtc_state;
-       int i;
-
-       if (DISPLAY_VER(display) < 20)
-               return false;
-
-       for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
-               if (!intel_crtc->active)
-                       continue;
-
-               if (crtc_state->vrr.enable)
-                       return false;
-       }
-
-       return true;
-}
-
-static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
-                                     struct intel_psr *psr)
-{
-       struct intel_display *display = to_intel_display(crtc_state);
-
-       return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
-               (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
-               !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
-}
-
-/*
- * DC5 entry is only possible if vblank interrupt is disabled
- * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
- * enabled encoders.
- */
-static bool
-intel_psr_is_dc5_entry_possible(struct intel_display *display,
-                               struct intel_atomic_state *state)
-{
-       struct intel_crtc *intel_crtc;
-       struct intel_crtc_state *crtc_state;
-       int i;
-
-       if ((display->power.domains.target_dc_state &
-            DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
-               return false;
-
-       for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
-               struct drm_crtc *crtc = &intel_crtc->base;
-               struct drm_vblank_crtc *vblank;
-               struct intel_encoder *encoder;
-
-               if (!intel_crtc->active)
-                       continue;
-
-               vblank = drm_crtc_vblank_crtc(crtc);
-
-               if (vblank->enabled)
-                       return false;
-
-               if (!crtc_state->has_psr)
-                       return false;
-
-               for_each_encoder_on_crtc(display->drm, crtc, encoder)
-                       if (encoder->type != INTEL_OUTPUT_EDP ||
-                           !CAN_PSR(enc_to_intel_dp(encoder)))
-                               return false;
-       }
-
-       return true;
-}
-
 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 {
        struct intel_display *display = to_intel_display(intel_dp);
@@ -1092,15 +1008,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
        u32 val = EDP_PSR2_ENABLE;
        u32 psr_val = 0;
 
-       /*
-        * Wa_22019444797
-        * TODO: Disable idle frames when vblank gets enabled while
-        * PSR2 is enabled
-        */
-       if (DISPLAY_VER(dev_priv) != 20 ||
-           !intel_dp->psr.is_dpkgc_configured ||
-           intel_dp->psr.is_dc5_entry_possible)
-               val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+       val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
 
        if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
                val |= EDP_SU_TRACK_ENABLE;
@@ -2815,20 +2723,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct intel_encoder *encoder;
-       bool dpkgc_configured = false, dc5_entry_possible = false;
-       bool wa_delayed_vblank_limit = false;
 
        if (!HAS_PSR(display))
                return;
 
-       if (DISPLAY_VER(display) == 20) {
-               dpkgc_configured = intel_psr_is_dpkgc_configured(display, state);
-               dc5_entry_possible =
-                       intel_psr_is_dc5_entry_possible(display, state);
-               wa_delayed_vblank_limit =
-                       intel_psr_check_wa_delayed_vblank(&new_crtc_state->hw.adjusted_mode);
-       }
-
        for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
                                             old_crtc_state->uapi.encoder_mask) {
                struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2837,12 +2735,6 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 
                mutex_lock(&psr->lock);
 
-               if (DISPLAY_VER(i915) == 20) {
-                       psr->is_dpkgc_configured = dpkgc_configured;
-                       psr->is_dc5_entry_possible = dc5_entry_possible;
-                       psr->is_wa_delayed_vblank_limit = wa_delayed_vblank_limit;
-               }
-
                /*
                 * Reasons to disable:
                 * - PSR disabled in new state
@@ -2850,7 +2742,6 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
                 * - Changing between PSR versions
                 * - Region Early Transport changing
                 * - Display WA #1136: skl, bxt
-                * - Display WA_22019444797
                 */
                needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
                needs_to_disable |= !new_crtc_state->has_psr;
@@ -2860,8 +2751,6 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
                        psr->su_region_et_enabled;
                needs_to_disable |= DISPLAY_VER(i915) < 11 &&
                        new_crtc_state->wm_level_disabled;
-               /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
-               needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
 
                if (psr->enabled && needs_to_disable)
                        intel_psr_disable_locked(intel_dp);
@@ -2902,12 +2791,6 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
                keep_disabled |= DISPLAY_VER(display) < 11 &&
                        crtc_state->wm_level_disabled;
 
-               /*
-                * Wa_22019444797
-                * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
-                */
-               keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
-
                if (!psr->enabled && !keep_disabled)
                        intel_psr_enable_locked(intel_dp, crtc_state);
                else if (psr->enabled && !crtc_state->wm_level_disabled)