}
/* init vga bits */
- vga_common_init(vga, OBJECT(s));
+ if (!vga_common_init(vga, OBJECT(s), errp)) {
+ return;
+ }
vga_init(vga, OBJECT(s), pci_address_space(dev),
pci_address_space_io(dev), true);
vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
return;
}
/* setup VGA */
- vga_common_init(&s->vga, OBJECT(dev));
+ if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
+ return;
+ }
cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
pci_address_space_io(dev));
s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
return;
}
s->global_vmstate = true;
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
isa_address_space(isadev),
isa_address_space_io(isadev));
qxl_init_ramsize(qxl);
vga->vbe_size = qxl->vgamem_size;
vga->vram_size_mb = qxl->vga.vram_size / MiB;
- vga_common_init(vga, OBJECT(dev));
+ vga_common_init(vga, OBJECT(dev), &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
vga_init(vga, OBJECT(dev),
pci_address_space(dev), pci_address_space_io(dev), false);
portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
const MemoryRegionPortio *vga_ports, *vbe_ports;
s->global_vmstate = true;
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
+
s->legacy_address_space = isa_address_space(isadev);
vga_io_memory = vga_init_io(s, OBJECT(dev), &vga_ports, &vbe_ports);
isa_register_portio_list(isadev, &d->portio_vga,
s->vga.bank_offset = 0;
s->vga.global_vmstate = true;
- vga_common_init(&s->vga, OBJECT(dev));
+ if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
+ return;
+ }
+
sysbus_init_mmio(sbd, &s->vga.vram);
s->vga.con = graphic_console_init(dev, 0, s->vga.hw_ops, &s->vga);
}
bool edid = false;
/* vga + console init */
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
true);
bool edid = false;
/* vga + console init */
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
/* mmio bar */
return val;
}
-void vga_common_init(VGACommonState *s, Object *obj)
+bool vga_common_init(VGACommonState *s, Object *obj, Error **errp)
{
int i, j, v, b;
+ Error *local_err = NULL;
for(i = 0;i < 256; i++) {
v = 0;
s->is_vbe_vmstate = 1;
memory_region_init_ram_nomigrate(&s->vram, obj, "vga.vram", s->vram_size,
- &error_fatal);
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return false;
+ }
vmstate_register_ram(&s->vram, s->global_vmstate ? NULL : DEVICE(obj));
xen_register_framebuffer(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
s->default_endian_fb = false;
#endif
vga_dirty_log_start(s);
+
+ return true;
}
static const MemoryRegionPortio vga_portio_list[] = {
return (v << 2) | (b << 1) | b;
}
-void vga_common_init(VGACommonState *s, Object *obj);
+bool vga_common_init(VGACommonState *s, Object *obj, Error **errp);
void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
MemoryRegion *address_space_io, bool init_vga_ports);
MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
/* init vga compat bits */
vga->vram_size_mb = 8;
- vga_common_init(vga, OBJECT(vpci_dev));
+ if (!vga_common_init(vga, OBJECT(vpci_dev), errp)) {
+ return;
+ }
vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
pci_address_space_io(&vpci_dev->pci_dev), true);
pci_register_bar(&vpci_dev->pci_dev, 0,
&error_fatal);
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
- vga_common_init(&s->vga, OBJECT(dev));
+ vga_common_init(&s->vga, OBJECT(dev), &error_fatal);
vga_init(&s->vga, OBJECT(dev), address_space, io, true);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
s->new_depth = 32;