net: stmmac: eswin: clear TXD and RXD delay registers during initialization

Clear the TXD and RXD delay control registers during EIC7700 DWMAC
initialization.

These registers may retain values programmed by the bootloader. If left
unchanged, residual delays can alter the effective RGMII timing seen by
the MAC and override the configuration described by the device tree.

This may violate the expected RGMII timing model and can cause link
instability or prevent the Ethernet controller from operating correctly.

Explicitly clearing these registers ensures that the MAC delay settings
are determined solely by the kernel configuration.

The corresponding register offsets are optional, and the registers are
only cleared when the offsets are provided in the device tree.

Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Link: https://patch.msgid.link/20260518022137.464-1-lizhi2@eswincomputing.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
index 63001c4acdb7ae91211e4ead370e09078433e4b8..541b279f08a17d29c3c31a0b8571c3ad621c9af2 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
@@ -46,7 +46,11 @@ struct eic7700_qos_priv {
        u32 eth_axi_lp_ctrl_offset;
        u32 eth_phy_ctrl_offset;
        u32 eth_clk_offset;
+       u32 eth_txd_offset;
+       u32 eth_rxd_offset;
        u32 eth_clk_dly_param;
+       bool has_txd_offset;
+       bool has_rxd_offset;
 };
 
 static int eic7700_clks_config(void *priv, bool enabled)
@@ -84,6 +88,12 @@ static int eic7700_dwmac_init(struct device *dev, void *priv)
        regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset,
                     EIC7700_ETH_CSYSREQ_VAL);
 
+       if (dwc->has_txd_offset)
+               regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0);
+
+       if (dwc->has_rxd_offset)
+               regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
+
        regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset,
                     dwc->eth_clk_dly_param);
 
@@ -190,6 +200,18 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
                return dev_err_probe(&pdev->dev, ret,
                                     "can't get eth_clk_offset\n");
 
+       ret = of_property_read_u32_index(pdev->dev.of_node,
+                                        "eswin,hsp-sp-csr",
+                                        4, &dwc_priv->eth_txd_offset);
+       if (!ret)
+               dwc_priv->has_txd_offset = true;
+
+       ret = of_property_read_u32_index(pdev->dev.of_node,
+                                        "eswin,hsp-sp-csr",
+                                        5, &dwc_priv->eth_rxd_offset);
+       if (!ret)
+               dwc_priv->has_rxd_offset = true;
+
        plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
        plat_dat->clks = devm_kcalloc(&pdev->dev,
                                      plat_dat->num_clks,