--- /dev/null
+From 2194bc7c39610be7cabe7456c5f63a570604f015 Mon Sep 17 00:00:00 2001
+From: Rajat Jain <rajatja@google.com>
+Date: Mon, 6 Jul 2020 16:32:40 -0700
+Subject: PCI: Add device even if driver attach failed
+
+From: Rajat Jain <rajatja@google.com>
+
+commit 2194bc7c39610be7cabe7456c5f63a570604f015 upstream.
+
+device_attach() returning failure indicates a driver error while trying to
+probe the device. In such a scenario, the PCI device should still be added
+in the system and be visible to the user.
+
+When device_attach() fails, merely warn about it and keep the PCI device in
+the system.
+
+This partially reverts ab1a187bba5c ("PCI: Check device_attach() return
+value always").
+
+Link: https://lore.kernel.org/r/20200706233240.3245512-1-rajatja@google.com
+Signed-off-by: Rajat Jain <rajatja@google.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: stable@vger.kernel.org # v4.6+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/bus.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+--- a/drivers/pci/bus.c
++++ b/drivers/pci/bus.c
+@@ -323,12 +323,8 @@ void pci_bus_add_device(struct pci_dev *
+
+ dev->match_driver = true;
+ retval = device_attach(&dev->dev);
+- if (retval < 0 && retval != -EPROBE_DEFER) {
++ if (retval < 0 && retval != -EPROBE_DEFER)
+ pci_warn(dev, "device attach failed (%d)\n", retval);
+- pci_proc_detach_device(dev);
+- pci_remove_sysfs_dev_files(dev);
+- return;
+- }
+
+ pci_dev_assign_added(dev, true);
+ }
--- /dev/null
+From dae68d7fd4930315389117e9da35b763f12238f9 Mon Sep 17 00:00:00 2001
+From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
+Date: Fri, 26 Jun 2020 19:42:34 +0200
+Subject: PCI: hotplug: ACPI: Fix context refcounting in acpiphp_grab_context()
+
+From: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+
+commit dae68d7fd4930315389117e9da35b763f12238f9 upstream.
+
+If context is not NULL in acpiphp_grab_context(), but the
+is_going_away flag is set for the device's parent, the reference
+counter of the context needs to be decremented before returning
+NULL or the context will never be freed, so make that happen.
+
+Fixes: edf5bf34d408 ("ACPI / dock: Use callback pointers from devices' ACPI hotplug contexts")
+Reported-by: Vasily Averin <vvs@virtuozzo.com>
+Cc: 3.15+ <stable@vger.kernel.org> # 3.15+
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/hotplug/acpiphp_glue.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+--- a/drivers/pci/hotplug/acpiphp_glue.c
++++ b/drivers/pci/hotplug/acpiphp_glue.c
+@@ -122,13 +122,21 @@ static struct acpiphp_context *acpiphp_g
+ struct acpiphp_context *context;
+
+ acpi_lock_hp_context();
++
+ context = acpiphp_get_context(adev);
+- if (!context || context->func.parent->is_going_away) {
+- acpi_unlock_hp_context();
+- return NULL;
++ if (!context)
++ goto unlock;
++
++ if (context->func.parent->is_going_away) {
++ acpiphp_put_context(context);
++ context = NULL;
++ goto unlock;
+ }
++
+ get_bridge(context->func.parent);
+ acpiphp_put_context(context);
++
++unlock:
+ acpi_unlock_hp_context();
+ return context;
+ }
--- /dev/null
+From 45beb31d3afb651bb5c41897e46bd4fa9980c51c Mon Sep 17 00:00:00 2001
+From: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Date: Tue, 28 Jul 2020 18:45:53 +0800
+Subject: PCI: Mark AMD Navi10 GPU rev 0x00 ATS as broken
+
+From: Kai-Heng Feng <kai.heng.feng@canonical.com>
+
+commit 45beb31d3afb651bb5c41897e46bd4fa9980c51c upstream.
+
+We are seeing AMD Radeon Pro W5700 doesn't work when IOMMU is enabled:
+
+ iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0]
+ iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01c0]
+
+The error also makes graphics driver fail to probe the device.
+
+It appears to be the same issue as commit 5e89cd303e3a ("PCI: Mark AMD
+Navi14 GPU rev 0xc5 ATS as broken") addresses, and indeed the same ATS
+quirk can workaround the issue.
+
+See-also: 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken")
+See-also: d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken")
+See-also: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken")
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208725
+Link: https://lore.kernel.org/r/20200728104554.28927-1-kai.heng.feng@canonical.com
+Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -5068,7 +5068,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SE
+ */
+ static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
+ {
+- if (pdev->device == 0x7340 && pdev->revision != 0xc5)
++ if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
++ (pdev->device == 0x7340 && pdev->revision != 0xc5))
+ return;
+
+ pci_info(pdev, "disabling ATS\n");
+@@ -5079,6 +5080,8 @@ static void quirk_amd_harvest_no_ats(str
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
+ /* AMD Iceland dGPU */
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
++/* AMD Navi10 dGPU */
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
+ /* AMD Navi14 dGPU */
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
+ #endif /* CONFIG_PCI_ATS */
--- /dev/null
+From 51c48b310183ab6ba5419edfc6a8de889cc04521 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Sat, 19 Jan 2019 11:35:04 -0600
+Subject: PCI: Probe bridge window attributes once at enumeration-time
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit 51c48b310183ab6ba5419edfc6a8de889cc04521 upstream.
+
+pci_bridge_check_ranges() determines whether a bridge supports the optional
+I/O and prefetchable memory windows and sets the flag bits in the bridge
+resources. This *could* be done once during enumeration except that the
+resource allocation code completely clears the flag bits, e.g., in the
+pci_assign_unassigned_bridge_resources() path.
+
+The problem with pci_bridge_check_ranges() in the resource allocation path
+is that we may allocate resources after devices have been claimed by
+drivers, and pci_bridge_check_ranges() *changes* the window registers to
+determine whether they're writable. This may break concurrent accesses to
+devices behind the bridge.
+
+Add a new pci_read_bridge_windows() to determine whether a bridge supports
+the optional windows, call it once during enumeration, remember the
+results, and change pci_bridge_check_ranges() so it doesn't touch the
+bridge windows but sets the flag bits based on those remembered results.
+
+Link: https://lore.kernel.org/linux-pci/1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com
+Link: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg02082.html
+Reported-by: Yandong Xu <xuyandong2@huawei.com>
+Tested-by: Yandong Xu <xuyandong2@huawei.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Michael S. Tsirkin <mst@redhat.com>
+Cc: Sagi Grimberg <sagi@grimberg.me>
+Cc: Ofer Hayut <ofer@lightbitslabs.com>
+Cc: Roy Shterman <roys@lightbitslabs.com>
+Cc: Keith Busch <keith.busch@intel.com>
+Cc: Zhou Wang <wangzhou1@hisilicon.com>
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208371
+Signed-off-by: Dima Stepanov <dimastep@yandex-team.ru>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/probe.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/pci/setup-bus.c | 45 +++--------------------------------------
+ include/linux/pci.h | 3 ++
+ 3 files changed, 59 insertions(+), 41 deletions(-)
+
+--- a/drivers/pci/probe.c
++++ b/drivers/pci/probe.c
+@@ -348,6 +348,57 @@ static void pci_read_bases(struct pci_de
+ }
+ }
+
++static void pci_read_bridge_windows(struct pci_dev *bridge)
++{
++ u16 io;
++ u32 pmem, tmp;
++
++ pci_read_config_word(bridge, PCI_IO_BASE, &io);
++ if (!io) {
++ pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
++ pci_read_config_word(bridge, PCI_IO_BASE, &io);
++ pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
++ }
++ if (io)
++ bridge->io_window = 1;
++
++ /*
++ * DECchip 21050 pass 2 errata: the bridge may miss an address
++ * disconnect boundary by one PCI data phase. Workaround: do not
++ * use prefetching on this device.
++ */
++ if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
++ return;
++
++ pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
++ if (!pmem) {
++ pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
++ 0xffe0fff0);
++ pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
++ pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
++ }
++ if (!pmem)
++ return;
++
++ bridge->pref_window = 1;
++
++ if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
++
++ /*
++ * Bridge claims to have a 64-bit prefetchable memory
++ * window; verify that the upper bits are actually
++ * writable.
++ */
++ pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
++ pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
++ 0xffffffff);
++ pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
++ pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
++ if (tmp)
++ bridge->pref_64_window = 1;
++ }
++}
++
+ static void pci_read_bridge_io(struct pci_bus *child)
+ {
+ struct pci_dev *dev = child->self;
+@@ -1712,6 +1763,7 @@ int pci_setup_device(struct pci_dev *dev
+ pci_read_irq(dev);
+ dev->transparent = ((dev->class & 0xff) == 1);
+ pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
++ pci_read_bridge_windows(dev);
+ set_pcie_hotplug_bridge(dev);
+ pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
+ if (pos) {
+--- a/drivers/pci/setup-bus.c
++++ b/drivers/pci/setup-bus.c
+@@ -735,58 +735,21 @@ int pci_claim_bridge_resource(struct pci
+ base/limit registers must be read-only and read as 0. */
+ static void pci_bridge_check_ranges(struct pci_bus *bus)
+ {
+- u16 io;
+- u32 pmem;
+ struct pci_dev *bridge = bus->self;
+- struct resource *b_res;
++ struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
+
+- b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
+ b_res[1].flags |= IORESOURCE_MEM;
+
+- pci_read_config_word(bridge, PCI_IO_BASE, &io);
+- if (!io) {
+- pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
+- pci_read_config_word(bridge, PCI_IO_BASE, &io);
+- pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
+- }
+- if (io)
++ if (bridge->io_window)
+ b_res[0].flags |= IORESOURCE_IO;
+
+- /* DECchip 21050 pass 2 errata: the bridge may miss an address
+- disconnect boundary by one PCI data phase.
+- Workaround: do not use prefetching on this device. */
+- if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
+- return;
+-
+- pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
+- if (!pmem) {
+- pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
+- 0xffe0fff0);
+- pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
+- pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
+- }
+- if (pmem) {
++ if (bridge->pref_window) {
+ b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
+- if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
+- PCI_PREF_RANGE_TYPE_64) {
++ if (bridge->pref_64_window) {
+ b_res[2].flags |= IORESOURCE_MEM_64;
+ b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
+ }
+ }
+-
+- /* double check if bridge does support 64 bit pref */
+- if (b_res[2].flags & IORESOURCE_MEM_64) {
+- u32 mem_base_hi, tmp;
+- pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
+- &mem_base_hi);
+- pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
+- 0xffffffff);
+- pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
+- if (!tmp)
+- b_res[2].flags &= ~IORESOURCE_MEM_64;
+- pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
+- mem_base_hi);
+- }
+ }
+
+ /* Helper function for sizing routines: find first available
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -373,6 +373,9 @@ struct pci_dev {
+ bool match_driver; /* Skip attaching driver */
+
+ unsigned int transparent:1; /* Subtractive decode bridge */
++ unsigned int io_window:1; /* Bridge has I/O window */
++ unsigned int pref_window:1; /* Bridge has pref mem window */
++ unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
+ unsigned int multifunction:1; /* Multi-function device */
+
+ unsigned int is_busmaster:1; /* Is busmaster */
--- /dev/null
+From de3c4bf648975ea0b1d344d811e9b0748907b47c Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 15 Jun 2020 23:06:04 +0200
+Subject: PCI: qcom: Add support for tx term offset for rev 2.1.0
+
+From: Ansuel Smith <ansuelsmth@gmail.com>
+
+commit de3c4bf648975ea0b1d344d811e9b0748907b47c upstream.
+
+Add tx term offset support to pcie qcom driver need in some revision of
+the ipq806x SoC. Ipq8064 needs tx term offset set to 7.
+
+Link: https://lore.kernel.org/r/20200615210608.21469-9-ansuelsmth@gmail.com
+Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
+Cc: stable@vger.kernel.org # v4.5+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -45,7 +45,13 @@
+ #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
+
+ #define PCIE20_PARF_PHY_CTRL 0x40
++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
++
+ #define PCIE20_PARF_PHY_REFCLK 0x4C
++#define PHY_REFCLK_SSP_EN BIT(16)
++#define PHY_REFCLK_USE_PAD BIT(12)
++
+ #define PCIE20_PARF_DBI_BASE_ADDR 0x168
+ #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
+ #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
+@@ -343,9 +349,18 @@ static int qcom_pcie_init_2_1_0(struct q
+ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+ }
+
++ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
++ /* set TX termination offset */
++ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
++ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
++ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
++ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
++ }
++
+ /* enable external reference clock */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+- val |= BIT(16);
++ val &= ~PHY_REFCLK_USE_PAD;
++ val |= PHY_REFCLK_SSP_EN;
+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+
+ ret = reset_control_deassert(res->phy_reset);
--- /dev/null
+From 5149901e9e6deca487c01cc434a3ac4125c7b00b Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 15 Jun 2020 23:06:03 +0200
+Subject: PCI: qcom: Define some PARF params needed for ipq8064 SoC
+
+From: Ansuel Smith <ansuelsmth@gmail.com>
+
+commit 5149901e9e6deca487c01cc434a3ac4125c7b00b upstream.
+
+Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
+needed on some ipq8064 based device (Netgear R7800 for example). Without
+this the system locks on kernel load.
+
+Link: https://lore.kernel.org/r/20200615210608.21469-8-ansuelsmth@gmail.com
+Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
+Cc: stable@vger.kernel.org # v4.5+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -76,6 +76,18 @@
+ #define DBI_RO_WR_EN 1
+
+ #define PERST_DELAY_US 1000
++/* PARF registers */
++#define PCIE20_PARF_PCS_DEEMPH 0x34
++#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
++#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
++#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
++
++#define PCIE20_PARF_PCS_SWING 0x38
++#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
++#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
++
++#define PCIE20_PARF_CONFIG_BITS 0x50
++#define PHY_RX0_EQ(x) ((x) << 24)
+
+ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
+ #define SLV_ADDR_SPACE_SZ 0x10000000
+@@ -275,6 +287,7 @@ static int qcom_pcie_init_2_1_0(struct q
+ struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
++ struct device_node *node = dev->of_node;
+ u32 val;
+ int ret;
+
+@@ -319,6 +332,17 @@ static int qcom_pcie_init_2_1_0(struct q
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
++ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
++ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
++ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
++ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
++ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
++ writel(PCS_SWING_TX_SWING_FULL(120) |
++ PCS_SWING_TX_SWING_LOW(120),
++ pcie->parf + PCIE20_PARF_PCS_SWING);
++ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
++ }
++
+ /* enable external reference clock */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ val |= BIT(16);
smb3-warn-on-confusing-error-scenario-with-sec-krb5.patch
genirq-affinity-make-affinity-setting-if-activated-opt-in.patch
+pci-hotplug-acpi-fix-context-refcounting-in-acpiphp_grab_context.patch
+pci-mark-amd-navi10-gpu-rev-0x00-ats-as-broken.patch
+pci-add-device-even-if-driver-attach-failed.patch
+pci-qcom-define-some-parf-params-needed-for-ipq8064-soc.patch
+pci-qcom-add-support-for-tx-term-offset-for-rev-2.1.0.patch
+pci-probe-bridge-window-attributes-once-at-enumeration-time.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
