drop arm patches from 6.12

diff --git a/queue-6.12/arm64-cputype-add-neoverse-v3ae-definitions.patch b/queue-6.12/arm64-cputype-add-neoverse-v3ae-definitions.patch
deleted file mode 100644 (file)
index 201a7f1..0000000
--- a/queue-6.12/arm64-cputype-add-neoverse-v3ae-definitions.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From stable+bounces-186003-greg=kroah.com@vger.kernel.org Thu Oct 16 13:12:49 2025
-From: Ryan Roberts <ryan.roberts@arm.com>
-Date: Thu, 16 Oct 2025 12:12:05 +0100
-Subject: arm64: cputype: Add Neoverse-V3AE definitions
-To: stable@vger.kernel.org
-Cc: Ryan Roberts <ryan.roberts@arm.com>, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>
-Message-ID: <20251016111208.3983300-2-ryan.roberts@arm.com>
-
-From: Mark Rutland <mark.rutland@arm.com>
-
-[ Upstream commit 3bbf004c4808e2c3241e5c1ad6cc102f38a03c39 ]
-
-Add cputype definitions for Neoverse-V3AE. These will be used for errata
-detection in subsequent patches.
-
-These values can be found in the Neoverse-V3AE TRM:
-
-  https://developer.arm.com/documentation/SDEN-2615521/9-0/
-
-... in section A.6.1 ("MIDR_EL1, Main ID Register").
-
-Signed-off-by: Mark Rutland <mark.rutland@arm.com>
-Cc: James Morse <james.morse@arm.com>
-Cc: Will Deacon <will@kernel.org>
-Cc: Catalin Marinas <catalin.marinas@arm.com>
-Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
-Signed-off-by: Will Deacon <will@kernel.org>
-[ Ryan: Trivial backport ]
-Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/include/asm/cputype.h |    2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/include/asm/cputype.h
-+++ b/arch/arm64/include/asm/cputype.h
-@@ -93,6 +93,7 @@
- #define ARM_CPU_PART_NEOVERSE_V2      0xD4F
- #define ARM_CPU_PART_CORTEX_A720      0xD81
- #define ARM_CPU_PART_CORTEX_X4                0xD82
-+#define ARM_CPU_PART_NEOVERSE_V3AE    0xD83
- #define ARM_CPU_PART_NEOVERSE_V3      0xD84
- #define ARM_CPU_PART_CORTEX_X925      0xD85
- #define ARM_CPU_PART_CORTEX_A725      0xD87
-@@ -180,6 +181,7 @@
- #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
- #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
- #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
-+#define MIDR_NEOVERSE_V3AE    MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)
- #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
- #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
- #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)

diff --git a/queue-6.12/arm64-errata-apply-workarounds-for-neoverse-v3ae.patch b/queue-6.12/arm64-errata-apply-workarounds-for-neoverse-v3ae.patch
deleted file mode 100644 (file)
index 105c4ca..0000000
--- a/queue-6.12/arm64-errata-apply-workarounds-for-neoverse-v3ae.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From stable+bounces-186004-greg=kroah.com@vger.kernel.org Thu Oct 16 13:12:53 2025
-From: Ryan Roberts <ryan.roberts@arm.com>
-Date: Thu, 16 Oct 2025 12:12:06 +0100
-Subject: arm64: errata: Apply workarounds for Neoverse-V3AE
-To: stable@vger.kernel.org
-Cc: Ryan Roberts <ryan.roberts@arm.com>, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>
-Message-ID: <20251016111208.3983300-3-ryan.roberts@arm.com>
-
-From: Mark Rutland <mark.rutland@arm.com>
-
-[ Upstream commit 0c33aa1804d101c11ba1992504f17a42233f0e11 ]
-
-Neoverse-V3AE is also affected by erratum #3312417, as described in its
-Software Developer Errata Notice (SDEN) document:
-
-  Neoverse V3AE (MP172) SDEN v9.0, erratum 3312417
-  https://developer.arm.com/documentation/SDEN-2615521/9-0/
-
-Enable the workaround for Neoverse-V3AE, and document this.
-
-Signed-off-by: Mark Rutland <mark.rutland@arm.com>
-Cc: James Morse <james.morse@arm.com>
-Cc: Will Deacon <will@kernel.org>
-Cc: Catalin Marinas <catalin.marinas@arm.com>
-Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
-Signed-off-by: Will Deacon <will@kernel.org>
-[ Ryan: Trivial backport ]
-Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- Documentation/arch/arm64/silicon-errata.rst |    2 ++
- arch/arm64/Kconfig                          |    1 +
- arch/arm64/kernel/cpu_errata.c              |    1 +
- 3 files changed, 4 insertions(+)
-
---- a/Documentation/arch/arm64/silicon-errata.rst
-+++ b/Documentation/arch/arm64/silicon-errata.rst
-@@ -198,6 +198,8 @@ stable kernels.
- +----------------+-----------------+-----------------+-----------------------------+
- | ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
- +----------------+-----------------+-----------------+-----------------------------+
-+| ARM            | Neoverse-V3AE   | #3312417        | ARM64_ERRATUM_3194386       |
-++----------------+-----------------+-----------------+-----------------------------+
- | ARM            | MMU-500         | #841119,826419  | N/A                         |
- +----------------+-----------------+-----------------+-----------------------------+
- | ARM            | MMU-600         | #1076982,1209401| N/A                         |
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -1111,6 +1111,7 @@ config ARM64_ERRATUM_3194386
-         * ARM Neoverse-V1 erratum 3324341
-         * ARM Neoverse V2 erratum 3324336
-         * ARM Neoverse-V3 erratum 3312417
-+        * ARM Neoverse-V3AE erratum 3312417
- 
-         On affected cores "MSR SSBS, #0" instructions may not affect
-         subsequent speculative instructions, which may permit unexepected
---- a/arch/arm64/kernel/cpu_errata.c
-+++ b/arch/arm64/kernel/cpu_errata.c
-@@ -455,6 +455,7 @@ static const struct midr_range erratum_s
-       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
-       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
-       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
-+      MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
-       {}
- };
- #endif

diff --git a/queue-6.12/series b/queue-6.12/series
index c69f987edeed402fed3c2fab09b15eba52fcc657..7ad2e113d9c07db1b78746df3ad3b002d17a5701 100644 (file)
--- a/queue-6.12/series
+++ b/queue-6.12/series
@@ -221,8 +221,6 @@ acpica-allow-to-skip-global-lock-initialization.patch
 ext4-free-orphan-info-with-kvfree.patch
 lib-crypto-curve25519-hacl64-disable-kasan-with-clang-17-and-older.patch
 selftests-mm-skip-soft-dirty-tests-when-config_mem_soft_dirty-is-disabled.patch
-arm64-cputype-add-neoverse-v3ae-definitions.patch
-arm64-errata-apply-workarounds-for-neoverse-v3ae.patch
 media-mc-clear-minor-number-before-put-device.patch
 squashfs-add-additional-inode-sanity-checking.patch
 squashfs-reject-negative-file-sizes-in-squashfs_read_inode.patch