]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
expand: Fix up ICE on VCE from _Complex types to _BitInt [PR117458]
authorJakub Jelinek <jakub@redhat.com>
Tue, 19 Nov 2024 09:26:44 +0000 (10:26 +0100)
committerJakub Jelinek <jakub@gcc.gnu.org>
Tue, 19 Nov 2024 09:26:44 +0000 (10:26 +0100)
extract_bit_field can't handle extraction of non-mode precision
from complex mode operands which don't live in memory, e.g. gen_lowpart
crashes on those.
The following patch in that case defers the extract_bit_field call
until op0 is forced into memory.

2024-11-19  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/117458
* expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Don't
call extract_bit_field if op0 has complex mode and isn't a MEM,
instead first force op0 into memory and then call extract_bit_field.

* gcc.dg/bitint-116.c: New test.

gcc/expr.cc
gcc/testsuite/gcc.dg/bitint-116.c [new file with mode: 0644]

index caa1a72ba0bef6c7c33c854b422cced771b90d1e..aa6ee85e7195d0bb28f7248aee0636657869c34f 100644 (file)
@@ -12505,7 +12505,9 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
        op0 = convert_modes (mode, GET_MODE (op0), op0,
                             TYPE_UNSIGNED (TREE_TYPE (treeop0)));
       /* If the output type is a bit-field type, do an extraction.  */
-      else if (reduce_bit_field && mode != BLKmode)
+      else if (reduce_bit_field
+              && mode != BLKmode
+              && (MEM_P (op0) || !COMPLEX_MODE_P (GET_MODE (op0))))
        return extract_bit_field (op0, TYPE_PRECISION (type), 0,
                                  TYPE_UNSIGNED (type), NULL_RTX,
                                  mode, mode, false, NULL);
@@ -12529,6 +12531,11 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
 
          emit_move_insn (target, op0);
          op0 = target;
+
+         if (reduce_bit_field && mode != BLKmode)
+           return extract_bit_field (op0, TYPE_PRECISION (type), 0,
+                                     TYPE_UNSIGNED (type), NULL_RTX,
+                                     mode, mode, false, NULL);
        }
 
       /* If OP0 is (now) a MEM, we need to deal with alignment issues.  If the
diff --git a/gcc/testsuite/gcc.dg/bitint-116.c b/gcc/testsuite/gcc.dg/bitint-116.c
new file mode 100644 (file)
index 0000000..9af5d72
--- /dev/null
@@ -0,0 +1,11 @@
+/* PR middle-end/117458 */
+/* { dg-do compile { target bitint } } */
+/* { dg-options "-std=c23 -O2" } */
+
+typedef _BitInt(33) B __attribute__((may_alias));
+
+_BitInt(33)
+foo (_Complex float x)
+{
+  return *(B *)&x;
+}