arm: testsuite: [MVE] Fix expected code for vadcq_m and vsbcq_m [PR122189]

The original versions of these tests only took into account code
generated with -mfloat-abi=hard.

Depending on how the toolchain is configured, arm_v8_1m_mve may use
-mfloat-abi-softfp, which generates a different instructions order.

Depending on the -mtune setting, the order can also vary, so the patch
adds -fno-schedule-insns -fno-schedule-insns2 to avoid such
maintenance issues.

In particular, this fixes the failures with:
 -mthumb -march=armv7e-m+fp.dp -mtune=cortex-m7 -mfloat-abi=hard -mfpu=auto
 -mthumb -march=armv6s-m -mtune=cortex-m0 -mfloat-abi=soft -mfpu=auto

gcc/testsuite/ChangeLog:

	PR target/122189
	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index c5a58782cdef1dcd28ad698f3c6e19893242f783..1802c20a39719347fe5113f93ff9ea1ad861ebc1 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vadct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vadct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 23908a4273dbf09978d6f5ea59a08a2d860932bf..64f221df8682e81c23ab597e8a12328f82b69a8f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vadct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vadct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 940e2edfcc5ead92a9bbfa680a6966a6faa63d21..da36d694ddfb8c58807a9ece6637880e085dd61b 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vsbct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vsbct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 478b938f8f74b9446e5e45606bf016620c988a4e..555690f5fb8060ba6b93438ffc949fd921cd9ce5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vsbct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
-**     ...
 **     bfi     (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 **     vmsr    FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:      @.*|)
 **     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
 **     vpst(?: @.*|)
 **     ...
 **     vsbct.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)