RISC-V: Add support for ssdbltrp and smdbltrp extension.

This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp
extensions, version1.0[2].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc

bfd/ChangeLog:

	* elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn
	  standard extensions.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/imply.d: Ditto.
	* testsuite/gas/riscv/imply.s: Ditto.
	* testsuite/gas/riscv/march-help.l: Ditto.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 45da83e69267a8c7a4be7eabf4529b948f9ef782..a6511f6558dc8604c2213f1b8e5907729cddd208 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1262,6 +1262,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smcntrpmf", "+zicsr", check_implicit_always},
   {"smstateen", "+ssstateen", check_implicit_always},
   {"smepmp", "+zicsr", check_implicit_always},
+  {"smdbltrp", "+zicsr", check_implicit_always},
 
   {"ssaia", "+zicsr", check_implicit_always},
   {"sscsrind", "+zicsr", check_implicit_always},
@@ -1272,6 +1273,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sstvala", "+zicsr", check_implicit_always},
   {"sstvecd", "+zicsr", check_implicit_always},
   {"ssu64xl", "+zicsr", check_implicit_always},
+  {"ssdbltrp", "+zicsr", check_implicit_always},
 
   {"svade", "+zicsr", check_implicit_always},
   {"svadu", "+zicsr", check_implicit_always},
@@ -1448,6 +1450,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"smepmp",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smrnmi",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smstateen",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"smdbltrp",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"ssaia",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"ssccptr",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sscsrind",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
@@ -1458,6 +1461,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sstvala",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sstvecd",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"ssu64xl",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"ssdbltrp",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svade",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svadu",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svbare",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },

diff --git a/gas/NEWS b/gas/NEWS
index 23eda334ec6b8d9f8c3d44447aa8815871203d44..269b63e2056b419ee66f97605c95b560777b8e2e 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -9,8 +9,8 @@
 
 * On x86 emulation support (for secondary targets) was dropped.
 
-* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi, CORE-V
-  (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive
+* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi, S[sm]dbltrp,
+  CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive
   extensions (xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf).
 
 Changes in 2.43:

diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 26eff8c650a21507e7e30b35dd96a28dcd6dacdc..474694d9071cc7a9c3f7500e6d4b22b4e6540068 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -80,6 +80,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smdbltrp1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0
@@ -89,6 +90,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sstvala1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sstvecd1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_ssu64xl1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_ssdbltrp1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_svade1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_svadu1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_svbare1p0

diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index dabb08d8c8b25ed7801c6312dbe4c1f6ce0c3ee6..790c6f335ee3d0906c76f58d2e25f06da96410d4 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -90,6 +90,8 @@ imply smcsrind
 imply smcntrpmf
 imply smstateen
 imply smepmp
+imply smdbltrp
+
 imply ssaia
 imply sscsrind
 imply sscofpmf
@@ -99,6 +101,7 @@ imply sstc
 imply sstvala
 imply sstvecd
 imply ssu64xl
+imply ssdbltrp
 
 imply svade
 imply svadu

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 71cccb7710261628f76f171aadcc1079fa391e8c..fd1174059e5dd89b1c908f9e7704e6fd5a005ad1 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -117,6 +117,7 @@ All available -march extensions for RISC-V:
        smepmp                                  1.0
        smrnmi                                  1.0
        smstateen                               1.0
+       smdbltrp                                1.0
        ssaia                                   1.0
        ssccptr                                 1.0
        sscsrind                                1.0
@@ -127,6 +128,7 @@ All available -march extensions for RISC-V:
        sstvala                                 1.0
        sstvecd                                 1.0
        ssu64xl                                 1.0
+       ssdbltrp                                1.0
        svade                                   1.0
        svadu                                   1.0
        svbare                                  1.0