aarch64.md (mov<mode>_aarch64): Change alternative 2 to use neon_move instead of...

gcc/
	* config/aarch64/aarch64.md (mov<mode>_aarch64): Change alternative 2
	to use neon_move instead of mov_imm.
	(movdi_aarch64): Change alternative 14 to use neon_move not fmov.
	(movtf_aarch64): Change alternative 4 to use neon_move_q not fconstd.
	* config/aarch64/aarch64.c (aarch64_valid_floating_const): Move
	aarch64_float_const_zero_rtx_p check before TFmode check.
	* config/aarch64/aarch64.md (movtf): Don't call force_reg if op1 is
	an fp zero.
	(movtf_aarch64): Separate ?rY alternative into two.  Adjust assembly
	code and attributes to match.  Change condition from register_operand
	to aarch64_reg_or_fp_zero for op1.  Change type for ldp from
	neon_load1_2reg to load2.  Change type for stp from neon_store1_2reg
	to store2.

From-SVN: r224493

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 48b9ca72059124147d720853c7b6bc768fdbfbf3..812cb7af07a90ba891a4e8518b48dd28f1004575 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2015-06-15  Jim Wilson  <jim.wilson@linaro.org>
+
+       * config/aarch64/aarch64.md (mov<mode>_aarch64): Change alternative 2
+       to use neon_move instead of mov_imm.
+       (movdi_aarch64): Change alternative 14 to use neon_move not fmov.
+       (movtf_aarch64): Change alternative 4 to use neon_move_q not fconstd.
+
+       * config/aarch64/aarch64.c (aarch64_valid_floating_const): Move
+       aarch64_float_const_zero_rtx_p check before TFmode check.
+       * config/aarch64/aarch64.md (movtf): Don't call force_reg if op1 is
+       an fp zero.
+       (movtf_aarch64): Separate ?rY alternative into two.  Adjust assembly
+       code and attributes to match.  Change condition from register_operand
+       to aarch64_reg_or_fp_zero for op1.  Change type for ldp from
+       neon_load1_2reg to load2.  Change type for stp from neon_store1_2reg
+       to store2.
+
 2015-06-15  Aldy Hernandez  <aldyh@redhat.com>
 
        PR debug/66535

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 0a0ad34668c68dd8ab148858689dee520a54df89..a79bb6a96572799181a5bff3c3818e294f87cb7a 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7417,16 +7417,13 @@ aarch64_valid_floating_const (machine_mode mode, rtx x)
   if (!CONST_DOUBLE_P (x))
     return false;
 
-  /* TODO: We could handle moving 0.0 to a TFmode register,
-     but first we would like to refactor the movtf_aarch64
-     to be more amicable to split moves properly and
-     correctly gate on TARGET_SIMD.  For now - reject all
-     constants which are not to SFmode or DFmode registers.  */
+  if (aarch64_float_const_zero_rtx_p (x))
+    return true;
+
+  /* We only handle moving 0.0 to a TFmode register.  */
   if (!(mode == SFmode || mode == DFmode))
     return false;
 
-  if (aarch64_float_const_zero_rtx_p (x))
-    return true;
   return aarch64_float_const_representable_p (x);
 }
 

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 11123d619ab3b21de92dd30904ba23245b864395..1efe57c91b10e47ab7511d089f7b4bb53f18f06e 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -827,7 +827,7 @@
        gcc_unreachable ();
      }
 }
-  [(set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
+  [(set_attr "type" "mov_reg,mov_imm,neon_move,load1,load1,store1,store1,\
                      neon_to_gp<q>,neon_from_gp<q>,neon_dup")
    (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")]
 )
@@ -912,7 +912,7 @@
        DONE;
     }"
   [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
-                     adr,adr,f_mcr,f_mrc,fmov,fmov")
+                     adr,adr,f_mcr,f_mrc,fmov,neon_move")
    (set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
    (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
 )
@@ -1040,18 +1040,20 @@
        FAIL;
      }
 
-    if (GET_CODE (operands[0]) == MEM)
+    if (GET_CODE (operands[0]) == MEM
+        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
+             && aarch64_float_const_zero_rtx_p (operands[1])))
       operands[1] = force_reg (TFmode, operands[1]);
   "
 )
 
 (define_insn "*movtf_aarch64"
   [(set (match_operand:TF 0
-        "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump")
+        "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump")
        (match_operand:TF 1
-        "general_operand"      " w,?r, ?r,w ,Y,Y ,m,w,Ump,?rY"))]
+        "general_operand"      " w,?r, ?r,w ,Y,Y ,m,w,Ump,?r ,Y"))]
   "TARGET_FLOAT && (register_operand (operands[0], TFmode)
-    || register_operand (operands[1], TFmode))"
+    || aarch64_reg_or_fp_zero (operands[1], TFmode))"
   "@
    orr\\t%0.16b, %1.16b, %1.16b
    #
@@ -1062,12 +1064,13 @@
    ldr\\t%q0, %1
    str\\t%q1, %0
    ldp\\t%0, %H0, %1
-   stp\\t%1, %H1, %0"
-  [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\
-                     f_loadd,f_stored,neon_load1_2reg,neon_store1_2reg")
-   (set_attr "length" "4,8,8,8,4,4,4,4,4,4")
-   (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*")
-   (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")]
+   stp\\t%1, %H1, %0
+   stp\\txzr, xzr, %0"
+  [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,fconstd,\
+                     f_loadd,f_stored,load2,store2,store2")
+   (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4")
+   (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*,*")
+   (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")]
 )
 
 (define_split