clk: imx93: Add IMX93_CLK_SPDIF_IPG clock

Split IMX93_CLK_SPDIF_IPG from IMX93_CLK_SPDIF_GATE
because the IMX93_CLK_SPDIF_GATE controls the gate
of IPG clock and root clock. Without this change,
disabling IMX93_CLK_SPDIF_GATE would also disable
the IPG clock, causing register access failures.

Fixes: 1c4a4f7362fd ("arm64: dts: imx93: Add audio device nodes")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20241119015805.3840606-3-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index 58a516dd385bf5736f5b55ebe8bc6bc423f2de4d..eb818db008fb69689fc29a5104504aef10ed9c58 100644 (file)
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -15,7 +15,7 @@
 
 #include "clk.h"
 
-#define IMX93_CLK_END 207
+#define IMX93_CLK_END 208
 
 #define PLAT_IMX93 BIT(0)
 #define PLAT_IMX91 BIT(1)
@@ -38,6 +38,7 @@ static u32 share_count_sai2;
 static u32 share_count_sai3;
 static u32 share_count_mub;
 static u32 share_count_pdm;
+static u32 share_count_spdif;
 
 static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
 static const char *parent_names[MAX_SEL][4] = {
@@ -252,7 +253,8 @@ static const struct imx93_clk_ccgr {
        { IMX93_CLK_MQS1_GATE,          "mqs1",         "sai1_root",            0x9b00, },
        { IMX93_CLK_MQS2_GATE,          "mqs2",         "sai3_root",            0x9b40, },
        { IMX93_CLK_AUD_XCVR_GATE,      "aud_xcvr",     "audio_xcvr_root",      0x9b80, },
-       { IMX93_CLK_SPDIF_GATE,         "spdif",        "spdif_root",           0x9c00, },
+       { IMX93_CLK_SPDIF_IPG,          "spdif_ipg_clk", "bus_wakeup_root",     0x9c00, 0, &share_count_spdif},
+       { IMX93_CLK_SPDIF_GATE,         "spdif",        "spdif_root",           0x9c00, 0, &share_count_spdif},
        { IMX93_CLK_HSIO_32K_GATE,      "hsio_32k",     "osc_32k",              0x9dc0, },
        { IMX93_CLK_ENET1_GATE,         "enet1",        "wakeup_axi_root",      0x9e00, 0, NULL, PLAT_IMX93, },
        { IMX93_CLK_ENET_QOS_GATE,      "enet_qos",     "wakeup_axi_root",      0x9e40, 0, NULL, PLAT_IMX93, },