fix up queue-4.14/arm64-move-post_ttbr_update_workaround-to-c-code.patch

diff --git a/queue-4.14/arm64-move-post_ttbr_update_workaround-to-c-code.patch b/queue-4.14/arm64-move-post_ttbr_update_workaround-to-c-code.patch
index 87522bf6ee98292459ef610fd62a20608e664457..52ceb0d2e5deaf239df2feec409d24b6723b43cd 100644 (file)
--- a/queue-4.14/arm64-move-post_ttbr_update_workaround-to-c-code.patch
+++ b/queue-4.14/arm64-move-post_ttbr_update_workaround-to-c-code.patch
@@ -5,7 +5,6 @@ Subject: [Variant 2/Spectre-v2] arm64: Move post_ttbr_update_workaround to C cod
 
 From: Marc Zyngier <marc.zyngier@arm.com>
 
-
 Commit 95e3de3590e3 upstream.
 
 We will soon need to invoke a CPU-specific function pointer after changing
@@ -18,15 +17,15 @@ Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 ---
- arch/arm64/include/asm/assembler.h |   23 -----------------------
+ arch/arm64/include/asm/assembler.h |   13 -------------
  arch/arm64/kernel/entry.S          |    2 +-
  arch/arm64/mm/context.c            |    9 +++++++++
  arch/arm64/mm/proc.S               |    3 +--
- 4 files changed, 11 insertions(+), 26 deletions(-)
+ 4 files changed, 11 insertions(+), 16 deletions(-)
 
 --- a/arch/arm64/include/asm/assembler.h
 +++ b/arch/arm64/include/asm/assembler.h
-@@ -481,29 +481,6 @@ alternative_endif
+@@ -481,19 +481,6 @@ alternative_endif
        mrs     \rd, sp_el0
        .endm
  
@@ -43,19 +42,9 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -#endif
 -      .endm
 -
--/**
-- * Errata workaround prior to disable MMU. Insert an ISB immediately prior
-- * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
-- */
--      .macro pre_disable_mmu_workaround
--#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
--      isb
--#endif
--      .endm
--
-       .macro  pte_to_phys, phys, pte
-       and     \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
-       .endm
+ /**
+  * Errata workaround prior to disable MMU. Insert an ISB immediately prior
+  * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
 --- a/arch/arm64/kernel/entry.S
 +++ b/arch/arm64/kernel/entry.S
 @@ -275,7 +275,7 @@ alternative_else_nop_endif