Fix bits and pieces needed to make self-checking-translations work

on amd64.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1265

diff --git a/VEX/priv/guest-generic/bb_to_IR.c b/VEX/priv/guest-generic/bb_to_IR.c
index 228d1f6b0f3ccd47176cf581f9476b6fccc78801..0d3fac981636fc0152a1b183a8840b14ccd5e756 100644 (file)
--- a/VEX/priv/guest-generic/bb_to_IR.c
+++ b/VEX/priv/guest-generic/bb_to_IR.c
@@ -43,7 +43,7 @@
 
 /* Forwards .. */
 __attribute((regparm(2)))
-static UInt genericg_compute_adler32 ( HWord addr, UInt len );
+static UInt genericg_compute_adler32 ( HWord addr, HWord len );
 
 
 /* Disassemble a complete basic block, starting at guest_IP_start, 
@@ -336,7 +336,7 @@ IRBB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
                    &genericg_compute_adler32,
                    mkIRExprVec_2( 
                       mkIRExpr_HWord( (HWord)guest_code ), 
-                      IRExpr_Const(IRConst_U32(len2check))
+                      mkIRExpr_HWord( (HWord)len2check )
                    )
                 ),
                 IRExpr_Const(IRConst_U32(adler32))
@@ -365,7 +365,7 @@ IRBB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
    once for every use of a self-checking translation, so it needs to
    be as fast as possible. */
 __attribute((regparm(2)))
-static UInt genericg_compute_adler32 ( HWord addr, UInt len )
+static UInt genericg_compute_adler32 ( HWord addr, HWord len )
 {
    UInt   s1 = 1;
    UInt   s2 = 0;

diff --git a/VEX/priv/host-amd64/hdefs.c b/VEX/priv/host-amd64/hdefs.c
index 8993f0f72fc274b9b56e42fe54e9a2fb76ba1f50..077bb0210a9806638651e2fc183e6dfd3ebb236b 100644 (file)
--- a/VEX/priv/host-amd64/hdefs.c
+++ b/VEX/priv/host-amd64/hdefs.c
@@ -2589,6 +2589,9 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
          case Ijk_NoDecode:
             *p++ = 0xBD;
             p = emit32(p, VEX_TRC_JMP_NODECODE); break;
+         case Ijk_TInval:
+            *p++ = 0xBD;
+            p = emit32(p, VEX_TRC_JMP_TINVAL); break;
          case Ijk_Ret:
          case Ijk_Call:
          case Ijk_Boring:

diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index bff3c2175bc75da03484b3ef07f6bad2e697d72d..c23185a79ac95f74cdbcf9dfdcfe50455331dfa8 100644 (file)
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -1576,14 +1576,20 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
       vassert(ty == e->Iex.CCall.retty);
 
       /* be very restrictive for now.  Only 64-bit ints allowed
-         for args, and 64 bits for return type. */
-      if (e->Iex.CCall.retty != Ity_I64)
+         for args, and 64 or 32 bits for return type. */
+      if (e->Iex.CCall.retty != Ity_I64 && e->Iex.CCall.retty != Ity_I32)
          goto irreducible;
 
       /* Marshal args, do the call. */
       doHelperCall( env, False, NULL, e->Iex.CCall.cee, e->Iex.CCall.args );
 
-      addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
+      /* Move to dst, and zero out the top 32 bits if the result type is
+         Ity_I32.  Probably overkill, but still .. */
+      if (e->Iex.CCall.retty == Ity_I64)
+         addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
+      else
+         addInstr(env, AMD64Instr_MovZLQ(hregAMD64_RAX(), dst));
+
       return dst;
    }