.33 mips patch

diff --git a/queue-2.6.33/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch b/queue-2.6.33/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch
new file mode 100644 (file)
index 0000000..d98faef
--- /dev/null
+++ b/queue-2.6.33/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch
@@ -0,0 +1,59 @@
+From 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 Mon Sep 17 00:00:00 2001
+From: Ralf Baechle <ralf@linux-mips.org>
+Date: Tue, 23 Mar 2010 17:56:38 +0100
+Subject: MIPS: Sibyte: Fix M3 TLB exception handler workaround.
+
+From: Ralf Baechle <ralf@linux-mips.org>
+
+commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 upstream.
+
+The M3 workaround needs to cmpare the region and VPN2 fields only.
+
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Cc: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/mips/mm/tlbex.c |   22 ++++++++++++++++------
+ 1 file changed, 16 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -741,10 +741,15 @@ static void __cpuinit build_r4000_tlb_re
+        * create the plain linear handler
+        */
+       if (bcm1250_m3_war()) {
+-              UASM_i_MFC0(&p, K0, C0_BADVADDR);
+-              UASM_i_MFC0(&p, K1, C0_ENTRYHI);
++              unsigned int segbits = 44;
++
++              uasm_i_dmfc0(&p, K0, C0_BADVADDR);
++              uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
+               uasm_i_xor(&p, K0, K0, K1);
+-              UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
++              uasm_i_dsrl32(&p, K1, K0, 62 - 32);
++              uasm_i_dsrl(&p, K0, K0, 12 + 1);
++              uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
++              uasm_i_or(&p, K0, K0, K1);
+               uasm_il_bnez(&p, &r, K0, label_leave);
+               /* No need for uasm_i_nop */
+       }
+@@ -1260,10 +1265,15 @@ static void __cpuinit build_r4000_tlb_lo
+       memset(relocs, 0, sizeof(relocs));
+ 
+       if (bcm1250_m3_war()) {
+-              UASM_i_MFC0(&p, K0, C0_BADVADDR);
+-              UASM_i_MFC0(&p, K1, C0_ENTRYHI);
++              unsigned int segbits = 44;
++
++              uasm_i_dmfc0(&p, K0, C0_BADVADDR);
++              uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
+               uasm_i_xor(&p, K0, K0, K1);
+-              UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
++              uasm_i_dsrl32(&p, K1, K0, 62 - 32);
++              uasm_i_dsrl(&p, K0, K0, 12 + 1);
++              uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
++              uasm_i_or(&p, K0, K0, K1);
+               uasm_il_bnez(&p, &r, K0, label_leave);
+               /* No need for uasm_i_nop */
+       }

diff --git a/queue-2.6.33/series b/queue-2.6.33/series
index a9ff1bf8059d9ef22163ac2d0792ff198b0bf0a2..2ea44ca164c51ba999fa5f6317f7d2bb98e60f19 100644 (file)
--- a/queue-2.6.33/series
+++ b/queue-2.6.33/series
@@ -136,3 +136,4 @@ sched-use-proper-type-in-sched_getaffinity.patch
 0008-KVM-Increase-NR_IOBUS_DEVS-limit-to-200.patch
 0009-KVM-x86-Fix-TSS-size-check-for-16-bit-tasks.patch
 x86-gart-disable-gart-explicitly-before-initialization.patch
+mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch