]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
6.12-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 2 Jul 2025 14:39:51 +0000 (16:39 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 2 Jul 2025 14:39:51 +0000 (16:39 +0200)
added patches:
net-phy-realtek-add-rtl8125d-internal-phy.patch
net-phy-realtek-merge-the-drivers-for-internal-nbase-t-phy-s.patch
r8169-add-support-for-rtl8125d.patch

queue-6.12/net-phy-realtek-add-rtl8125d-internal-phy.patch [new file with mode: 0644]
queue-6.12/net-phy-realtek-merge-the-drivers-for-internal-nbase-t-phy-s.patch [new file with mode: 0644]
queue-6.12/r8169-add-support-for-rtl8125d.patch [new file with mode: 0644]
queue-6.12/series

diff --git a/queue-6.12/net-phy-realtek-add-rtl8125d-internal-phy.patch b/queue-6.12/net-phy-realtek-add-rtl8125d-internal-phy.patch
new file mode 100644 (file)
index 0000000..5756e24
--- /dev/null
@@ -0,0 +1,35 @@
+From 8989bad541133c43550bff2b80edbe37b8fb9659 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Thu, 17 Oct 2024 18:01:13 +0200
+Subject: net: phy: realtek: add RTL8125D-internal PHY
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+commit 8989bad541133c43550bff2b80edbe37b8fb9659 upstream.
+
+The first boards show up with Realtek's RTL8125D. This MAC/PHY chip
+comes with an integrated 2.5Gbps PHY with ID 0x001cc841. It's not
+clear yet whether there's an external version of this PHY and how
+Realtek calls it, therefore use the numeric id for now.
+
+Link: https://lore.kernel.org/netdev/2ada65e1-5dfa-456c-9334-2bc51272e9da@gmail.com/T/
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Message-ID: <7d2924de-053b-44d2-a479-870dc3878170@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Mathieu Tortuyaux <mtortuyaux@microsoft.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/phy/realtek.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -1114,6 +1114,7 @@ static int rtl_internal_nbaset_match_phy
+       case RTL_GENERIC_PHYID:
+       case RTL_8221B:
+       case RTL_8251B:
++      case 0x001cc841:
+               break;
+       default:
+               return false;
diff --git a/queue-6.12/net-phy-realtek-merge-the-drivers-for-internal-nbase-t-phy-s.patch b/queue-6.12/net-phy-realtek-merge-the-drivers-for-internal-nbase-t-phy-s.patch
new file mode 100644 (file)
index 0000000..9ae0a71
--- /dev/null
@@ -0,0 +1,141 @@
+From f87a17ed3b51fba4dfdd8f8b643b5423a85fc551 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Tue, 15 Oct 2024 07:47:14 +0200
+Subject: net: phy: realtek: merge the drivers for internal NBase-T PHY's
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+commit f87a17ed3b51fba4dfdd8f8b643b5423a85fc551 upstream.
+
+The Realtek RTL8125/RTL8126 NBase-T MAC/PHY chips have internal PHY's
+which are register-compatible, at least for the registers we use here.
+So let's use just one PHY driver to support all of them.
+These internal PHY's exist also as external C45 PHY's, but on the
+internal PHY's no access to MMD registers is possible. This can be
+used to differentiate between the internal and external version.
+
+As a side effect the drivers for two now external-only drivers don't
+require read_mmd/write_mmd hooks any longer.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Link: https://patch.msgid.link/c57081a6-811f-4571-ab35-34f4ca6de9af@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Mathieu Tortuyaux <mtortuyaux@microsoft.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/phy/realtek.c |   53 +++++++++++++++++++++++++++++++++++++---------
+ 1 file changed, 43 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -92,6 +92,7 @@
+ #define RTL_GENERIC_PHYID                     0x001cc800
+ #define RTL_8211FVD_PHYID                     0x001cc878
++#define RTL_8221B                             0x001cc840
+ #define RTL_8221B_VB_CG                               0x001cc849
+ #define RTL_8221B_VN_CG                               0x001cc84a
+ #define RTL_8251B                             0x001cc862
+@@ -1040,6 +1041,23 @@ static bool rtlgen_supports_2_5gbps(stru
+       return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
+ }
++/* On internal PHY's MMD reads over C22 always return 0.
++ * Check a MMD register which is known to be non-zero.
++ */
++static bool rtlgen_supports_mmd(struct phy_device *phydev)
++{
++      int val;
++
++      phy_lock_mdio_bus(phydev);
++      __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
++      __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
++      __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
++      val = __phy_read(phydev, MII_MMD_DATA);
++      phy_unlock_mdio_bus(phydev);
++
++      return val > 0;
++}
++
+ static int rtlgen_match_phy_device(struct phy_device *phydev)
+ {
+       return phydev->phy_id == RTL_GENERIC_PHYID &&
+@@ -1049,7 +1067,8 @@ static int rtlgen_match_phy_device(struc
+ static int rtl8226_match_phy_device(struct phy_device *phydev)
+ {
+       return phydev->phy_id == RTL_GENERIC_PHYID &&
+-             rtlgen_supports_2_5gbps(phydev);
++             rtlgen_supports_2_5gbps(phydev) &&
++             rtlgen_supports_mmd(phydev);
+ }
+ static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
+@@ -1061,6 +1080,11 @@ static int rtlgen_is_c45_match(struct ph
+               return !is_c45 && (id == phydev->phy_id);
+ }
++static int rtl8221b_match_phy_device(struct phy_device *phydev)
++{
++      return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
++}
++
+ static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
+ {
+       return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
+@@ -1081,9 +1105,21 @@ static int rtl8221b_vn_cg_c45_match_phy_
+       return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
+ }
+-static int rtl8251b_c22_match_phy_device(struct phy_device *phydev)
++static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
+ {
+-      return rtlgen_is_c45_match(phydev, RTL_8251B, false);
++      if (phydev->is_c45)
++              return false;
++
++      switch (phydev->phy_id) {
++      case RTL_GENERIC_PHYID:
++      case RTL_8221B:
++      case RTL_8251B:
++              break;
++      default:
++              return false;
++      }
++
++      return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
+ }
+ static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
+@@ -1345,10 +1381,8 @@ static struct phy_driver realtek_drvs[]
+               .resume         = rtlgen_resume,
+               .read_page      = rtl821x_read_page,
+               .write_page     = rtl821x_write_page,
+-              .read_mmd       = rtl822x_read_mmd,
+-              .write_mmd      = rtl822x_write_mmd,
+       }, {
+-              PHY_ID_MATCH_EXACT(0x001cc840),
++              .match_phy_device = rtl8221b_match_phy_device,
+               .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
+               .get_features   = rtl822x_get_features,
+               .config_aneg    = rtl822x_config_aneg,
+@@ -1359,8 +1393,6 @@ static struct phy_driver realtek_drvs[]
+               .resume         = rtlgen_resume,
+               .read_page      = rtl821x_read_page,
+               .write_page     = rtl821x_write_page,
+-              .read_mmd       = rtl822x_read_mmd,
+-              .write_mmd      = rtl822x_write_mmd,
+       }, {
+               PHY_ID_MATCH_EXACT(0x001cc838),
+               .name           = "RTL8226-CG 2.5Gbps PHY",
+@@ -1438,8 +1470,9 @@ static struct phy_driver realtek_drvs[]
+               .read_page      = rtl821x_read_page,
+               .write_page     = rtl821x_write_page,
+       }, {
+-              .match_phy_device = rtl8251b_c22_match_phy_device,
+-              .name           = "RTL8126A-internal 5Gbps PHY",
++              .match_phy_device = rtl_internal_nbaset_match_phy_device,
++              .name           = "Realtek Internal NBASE-T PHY",
++              .flags          = PHY_IS_INTERNAL,
+               .get_features   = rtl822x_get_features,
+               .config_aneg    = rtl822x_config_aneg,
+               .read_status    = rtl822x_read_status,
diff --git a/queue-6.12/r8169-add-support-for-rtl8125d.patch b/queue-6.12/r8169-add-support-for-rtl8125d.patch
new file mode 100644 (file)
index 0000000..71f1fab
--- /dev/null
@@ -0,0 +1,149 @@
+From f75d1fbe7809bc5ed134204b920fd9e2fc5db1df Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Thu, 24 Oct 2024 22:42:33 +0200
+Subject: r8169: add support for RTL8125D
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+commit f75d1fbe7809bc5ed134204b920fd9e2fc5db1df upstream.
+
+This adds support for new chip version RTL8125D, which can be found on
+boards like Gigabyte X870E AORUS ELITE WIFI7. Firmware rtl8125d-1.fw
+for this chip version is available in linux-firmware already.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://patch.msgid.link/d0306912-e88e-4c25-8b5d-545ae8834c0c@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Mathieu Tortuyaux <mtortuyaux@microsoft.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/realtek/r8169.h            |    1 +
+ drivers/net/ethernet/realtek/r8169_main.c       |   23 ++++++++++++++++-------
+ drivers/net/ethernet/realtek/r8169_phy_config.c |   10 ++++++++++
+ 3 files changed, 27 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/realtek/r8169.h
++++ b/drivers/net/ethernet/realtek/r8169.h
+@@ -68,6 +68,7 @@ enum mac_version {
+       /* support for RTL_GIGA_MAC_VER_60 has been removed */
+       RTL_GIGA_MAC_VER_61,
+       RTL_GIGA_MAC_VER_63,
++      RTL_GIGA_MAC_VER_64,
+       RTL_GIGA_MAC_VER_65,
+       RTL_GIGA_MAC_VER_66,
+       RTL_GIGA_MAC_NONE
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -55,6 +55,7 @@
+ #define FIRMWARE_8107E_2      "rtl_nic/rtl8107e-2.fw"
+ #define FIRMWARE_8125A_3      "rtl_nic/rtl8125a-3.fw"
+ #define FIRMWARE_8125B_2      "rtl_nic/rtl8125b-2.fw"
++#define FIRMWARE_8125D_1      "rtl_nic/rtl8125d-1.fw"
+ #define FIRMWARE_8126A_2      "rtl_nic/rtl8126a-2.fw"
+ #define FIRMWARE_8126A_3      "rtl_nic/rtl8126a-3.fw"
+@@ -138,6 +139,7 @@ static const struct {
+       [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
+       /* reserve 62 for CFG_METHOD_4 in the vendor driver */
+       [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
++      [RTL_GIGA_MAC_VER_64] = {"RTL8125D",            FIRMWARE_8125D_1},
+       [RTL_GIGA_MAC_VER_65] = {"RTL8126A",            FIRMWARE_8126A_2},
+       [RTL_GIGA_MAC_VER_66] = {"RTL8126A",            FIRMWARE_8126A_3},
+ };
+@@ -707,6 +709,7 @@ MODULE_FIRMWARE(FIRMWARE_8168FP_3);
+ MODULE_FIRMWARE(FIRMWARE_8107E_2);
+ MODULE_FIRMWARE(FIRMWARE_8125A_3);
+ MODULE_FIRMWARE(FIRMWARE_8125B_2);
++MODULE_FIRMWARE(FIRMWARE_8125D_1);
+ MODULE_FIRMWARE(FIRMWARE_8126A_2);
+ MODULE_FIRMWARE(FIRMWARE_8126A_3);
+@@ -2098,10 +2101,7 @@ static void rtl_set_eee_txidle_timer(str
+               tp->tx_lpi_timer = timer_val;
+               r8168_mac_ocp_write(tp, 0xe048, timer_val);
+               break;
+-      case RTL_GIGA_MAC_VER_61:
+-      case RTL_GIGA_MAC_VER_63:
+-      case RTL_GIGA_MAC_VER_65:
+-      case RTL_GIGA_MAC_VER_66:
++      case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
+               tp->tx_lpi_timer = timer_val;
+               RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
+               break;
+@@ -2233,6 +2233,9 @@ static enum mac_version rtl8169_get_mac_
+               { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 },
+               { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
++              /* 8125D family. */
++              { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 },
++
+               /* 8125B family. */
+               { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
+@@ -2500,9 +2503,7 @@ static void rtl_init_rxcfg(struct rtl816
+       case RTL_GIGA_MAC_VER_61:
+               RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
+               break;
+-      case RTL_GIGA_MAC_VER_63:
+-      case RTL_GIGA_MAC_VER_65:
+-      case RTL_GIGA_MAC_VER_66:
++      case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:
+               RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
+                       RX_PAUSE_SLOT_ON);
+               break;
+@@ -3840,6 +3841,12 @@ static void rtl_hw_start_8125b(struct rt
+       rtl_hw_start_8125_common(tp);
+ }
++static void rtl_hw_start_8125d(struct rtl8169_private *tp)
++{
++      rtl_set_def_aspm_entry_latency(tp);
++      rtl_hw_start_8125_common(tp);
++}
++
+ static void rtl_hw_start_8126a(struct rtl8169_private *tp)
+ {
+       rtl_disable_zrxdc_timeout(tp);
+@@ -3889,6 +3896,7 @@ static void rtl_hw_config(struct rtl8169
+               [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
+               [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
+               [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
++              [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
+               [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
+               [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a,
+       };
+@@ -3906,6 +3914,7 @@ static void rtl_hw_start_8125(struct rtl
+       /* disable interrupt coalescing */
+       switch (tp->mac_version) {
+       case RTL_GIGA_MAC_VER_61:
++      case RTL_GIGA_MAC_VER_64:
+               for (i = 0xa00; i < 0xb00; i += 4)
+                       RTL_W32(tp, i, 0);
+               break;
+--- a/drivers/net/ethernet/realtek/r8169_phy_config.c
++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
+@@ -1104,6 +1104,15 @@ static void rtl8125b_hw_phy_config(struc
+       rtl8125b_config_eee_phy(phydev);
+ }
++static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
++                                 struct phy_device *phydev)
++{
++      r8169_apply_firmware(tp);
++      rtl8125_legacy_force_mode(phydev);
++      rtl8168g_disable_aldps(phydev);
++      rtl8125b_config_eee_phy(phydev);
++}
++
+ static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
+                                  struct phy_device *phydev)
+ {
+@@ -1160,6 +1169,7 @@ void r8169_hw_phy_config(struct rtl8169_
+               [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config,
+               [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
+               [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
++              [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
+               [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,
+               [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config,
+       };
index d4c030ed650981562e819b34120ad0e89c325128..fd8002791f8972a45c9b8ff638f74af1c8c9f53b 100644 (file)
@@ -198,3 +198,6 @@ io_uring-net-always-use-current-transfer-count-for-buffer-put.patch
 io_uring-net-mark-iov-as-dynamically-allocated-even-for-single-segments.patch
 io_uring-kbuf-flag-partial-buffer-mappings.patch
 mm-vma-reset-vma-iterator-on-commit_merge-oom-failure.patch
+r8169-add-support-for-rtl8125d.patch
+net-phy-realtek-merge-the-drivers-for-internal-nbase-t-phy-s.patch
+net-phy-realtek-add-rtl8125d-internal-phy.patch