drm/amd/display: fix a typo which causes an incorrect ODM combine setup

[why]
A recent change for ODM combine refactor contains a typo which causes ODM
combine mode programmed incorrectly.

Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index d085c9ff9d382a8cce60816fc5201b439c06b8c5..42c3c440ed8908a4e0e076c64968a83536e38eb4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -854,7 +854,7 @@ enum dc_status dcn20_enable_stream_timing(
 
        opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);
        for (i = 0; i < opp_cnt; i++)
-               opp_inst[opp_cnt] = opp_heads[i]->stream_res.opp->inst;
+               opp_inst[i] = opp_heads[i]->stream_res.opp->inst;
 
        odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
        last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);