return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
}
-static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
+static int gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
{
alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
+
+ return 0;
}
static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
}
-static void gpio1_set(struct gpio_chip *chip,
+static int gpio1_set(struct gpio_chip *chip,
unsigned offset, int value)
{
alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
+
+ return 0;
}
static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
.direction_input = gpio1_direction_input,
.direction_output = gpio1_direction_output,
.get = gpio1_get,
- .set = gpio1_set,
+ .set_rv = gpio1_set,
.to_irq = gpio1_to_irq,
.base = ALCHEMY_GPIO1_BASE,
.ngpio = ALCHEMY_GPIO1_NUM,
.direction_input = gpio2_direction_input,
.direction_output = gpio2_direction_output,
.get = gpio2_get,
- .set = gpio2_set,
+ .set_rv = gpio2_set,
.to_irq = gpio2_to_irq,
.base = ALCHEMY_GPIO2_BASE,
.ngpio = ALCHEMY_GPIO2_NUM,