i386: Decouple AMX-AVX512 from AVX10.2 and imply AVX512F

In ISE058, the AVX10.2 imply is removed from AMX-AVX512. This
leads to re-consideration on the imply for AMX-AVX512.

Since it is using zmm register and using zmm register only, we
need to at least imply AVX512F. AVX512VL is not needed.

On the other hand, if we imply AVX10.1 for AMX-AVX512, it will
cause -mno-avx10.1 disabling AMX-AVX512. This would be a surprise
for users.

Based on the two reasons above, the patch is decoupling AMX-AVX512
from AVX10.2 and imply AVX512F.

gcc/ChangeLog:

	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AMX_AVX512_SET): Do not set AVX10.2.
	(OPTION_MASK_ISA2_AVX10_2_UNSET): Remove AMX-AVX512 unset.
	(OPTION_MASK_ISA2_AVX512F_UNSET): Unset AMX-AVX512.
	(ix86_handle_option): Imply AVX512F for AMX-AVX512.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/amxavx512-cvtrowd2ps-2.c: Add -mavx512fp16 to
	use FP16 related intrins for convert.
	* gcc.target/i386/amxavx512-cvtrowps2bf16-2.c: Ditto.
	* gcc.target/i386/amxavx512-cvtrowps2ph-2.c: Ditto.
	* gcc.target/i386/amxavx512-movrow-2.c: Ditto.

diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index dfcd4e9a7276918493167bf9ad5c3523ef3c99e5..9e807e4b8f66acf0be6047159111ca00d1e7689e 100644 (file)
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -131,8 +131,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AVX10_2_SET \
   (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
 #define OPTION_MASK_ISA2_AMX_AVX512_SET \
-  (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AVX10_2_SET \
-   | OPTION_MASK_ISA2_AMX_AVX512)
+  (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_AVX512)
 #define OPTION_MASK_ISA2_AMX_TF32_SET \
   (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_TF32)
 #define OPTION_MASK_ISA2_AMX_TRANSPOSE_SET \
@@ -328,8 +327,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
 #define OPTION_MASK_ISA2_AVX10_1_UNSET \
   (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET)
-#define OPTION_MASK_ISA2_AVX10_2_UNSET \
-  (OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
+#define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
 #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
 #define OPTION_MASK_ISA2_AMX_TF32_UNSET OPTION_MASK_ISA2_AMX_TF32
 #define OPTION_MASK_ISA2_AMX_TRANSPOSE_UNSET OPTION_MASK_ISA2_AMX_TRANSPOSE
@@ -379,7 +377,8 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AVX512F_UNSET \
   (OPTION_MASK_ISA2_AVX512BW_UNSET \
    | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
-   | OPTION_MASK_ISA2_AVX10_1_UNSET)
+   | OPTION_MASK_ISA2_AVX10_1_UNSET \
+   | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
   OPTION_MASK_ISA2_SSE_UNSET
 #define OPTION_MASK_ISA2_AVX_UNSET \
@@ -1374,8 +1373,8 @@ ix86_handle_option (struct gcc_options *opts,
        {
          opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
          opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
-         opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
-         opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
+         opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
+         opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
        }
       else
        {

diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c
index cfd5644c5bb1f9cfff4b208bf6b4b7d7c71b4b9c..c9a2d19a726ad61a3353db79fc46f0f4501ba134 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c
+++ b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { ! ia32 } } } */
 /* { dg-require-effective-target amx_avx512 } */
-/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */
+/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */
 #define AMX_AVX512
 #define DO_TEST test_amx_avx512_cvtrowd2ps
 void test_amx_avx512_cvtrowd2ps();

diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c
index acd5f76c96cb85f1982825277c2a80553370192d..2014ec6f81115be69b8854c40b32b5af1ac6ed54 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c
+++ b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { ! ia32 } } } */
 /* { dg-require-effective-target amx_avx512 } */
-/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */
+/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */
 #define AMX_AVX512
 #define DO_TEST test_amx_avx512_cvtrowps2bf16
 void test_amx_avx512_cvtrowps2bf16();

diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c
index 1fd28def9342a37fb3f5067b4f7a4c5085220854..ca53ed009cf615f234bed8353c3a54b5c7efe7ef 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c
+++ b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { ! ia32 } } } */
 /* { dg-require-effective-target amx_avx512 } */
-/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */
+/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */
 #define AMX_AVX512
 #define DO_TEST test_amx_avx512_cvtrowps2ph
 void test_amx_avx512_cvtrowps2ph();

diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c
index ea28d82507ef62e008e5849eb8c8f8f89c7ea2cc..b2dee1474bb97117d4de17be77dcf6c2a637a715 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c
+++ b/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { ! ia32 } } } */
 /* { dg-require-effective-target amx_avx512 } */
-/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */
+/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */
 #define AMX_AVX512
 #define DO_TEST test_amx_avx512_movrow
 void test_amx_avx512_movrow();