]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153
authorMarc Kleine-Budde <mkl@pengutronix.de>
Thu, 7 Aug 2025 06:09:31 +0000 (08:09 +0200)
committerAlexandre Torgue <alexandre.torgue@foss.st.com>
Mon, 15 Sep 2025 15:51:30 +0000 (17:51 +0200)
On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external
shared reset in the RCC. Add the reset to both m_can nodes.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-2-f69ebbfced1f@pengutronix.de
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
arch/arm/boot/dts/st/stm32mp153.dtsi

index 4640dafb1598c2701b6db1903530636a78e60369..92794b942ab22920c72859970127db4f01e53e5d 100644 (file)
@@ -40,6 +40,7 @@
                interrupt-names = "int0", "int1";
                clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
                clock-names = "hclk", "cclk";
+               resets = <&rcc FDCAN_R>;
                bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
                access-controllers = <&etzpc 62>;
                status = "disabled";
@@ -54,6 +55,7 @@
                interrupt-names = "int0", "int1";
                clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
                clock-names = "hclk", "cclk";
+               resets = <&rcc FDCAN_R>;
                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
                access-controllers = <&etzpc 62>;
                status = "disabled";