Merge tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull interrupt subsystem updates from Thomas Gleixner:
 "Core code:

   - Interrupt storm detection for the lockup watchdog:

     Lockups which are caused by interrupt storms are not easy to debug
     because there is no information about the events which make the
     lockup detector trigger.

     To make this more user friendly, provide an extenstion to interrupt
     statistics which allows to take snapshots and an interface to
     retrieve the delta to the snapshot. Use this new mechanism in the
     watchdog code to do a two stage lockup analysis by taking the
     snapshot and printing the deltas for the topmost active interrupts
     on the second trigger.

     Note: This contains both the interrupt and the watchdog changes as
     the latter depend on the former obviously.

   - Avoid summation loops in the /proc/interrupts output and use the
     global counter when possible

   - Skip suspended interrupts on CPU hotplug operations to ensure that
     they are not delivered before the system resumes the device drivers
     when coming out of suspend.

   - On CPU hot-unplug interrupts which are affine to the outgoing CPU
     are migrated to a different CPU in the affinity mask. This can fail
     when the CPUs have no vectors left. Instead of giving up try to
     migrate it to any online CPU and thereby breaking the affinity
     setting in order to prevent a stale device interrupt which targets
     an offline CPU

   - The usual small cleanups

  Driver code:

   - Support for the RISCV AIA MSI controller

   - Make the interrupt allocation for the Loongson PCH controller more
     flexible to prevent vector exhaustion

   - The usual set of cleanups and fixes all over the place"

* tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (51 commits)
  irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_alloc
  cpuidle: Avoid explicit cpumask allocation on stack
  irqchip/sifive-plic: Avoid explicit cpumask allocation on stack
  irqchip/riscv-aplic-direct: Avoid explicit cpumask allocation on stack
  irqchip/loongson-eiointc: Avoid explicit cpumask allocation on stack
  irqchip/gic-v3-its: Avoid explicit cpumask allocation on stack
  irqchip/irq-bcm6345-l1: Avoid explicit cpumask allocation on stack
  cpumask: Introduce cpumask_first_and_and()
  irqchip/irq-brcmstb-l2: Avoid saving mask on shutdown
  genirq: Reuse irq_is_nmi()
  genirq/cpuhotplug: Retry with cpu_online_mask when migration fails
  genirq/cpuhotplug: Skip suspended interrupts when restoring affinity
  arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251
  arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251
  ARM: dts: stm32: List exti parent interrupts on stm32mp131
  ARM: dts: stm32: List exti parent interrupts on stm32mp151
  arm64: Kconfig.platforms: Enable STM32_EXTI for ARCH_STM32
  irqchip/stm32-exti: Mark events reserved with RIF configuration check
  irqchip/stm32-exti: Skip secure events
  irqchip/stm32-exti: Convert driver to standard PM
  ...

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm/boot/dts/st/stm32mp131.dtsi
index ecfa120827ba012f275a8ccc9bd512961c8e7359,c432fe109cbec3b9736f67988c5431178e16e503..6704ceef284d31dfef66c1093eaf338ebcf99427
--- 1/arch/arm/boot/dts/st/stm32mp131.dtsi
--- 2/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@@ -758,32 -1092,8 +758,32 @@@
                                 <&scmi_clk CK_SCMI_LSI>;
                };
  
 +              pwr_regulators: pwr@50001000 {
 +                      compatible = "st,stm32mp1,pwr-reg";
 +                      reg = <0x50001000 0x10>;
 +                      status = "disabled";
 +
 +                      reg11: reg11 {
 +                              regulator-name = "reg11";
 +                              regulator-min-microvolt = <1100000>;
 +                              regulator-max-microvolt = <1100000>;
 +                      };
 +
 +                      reg18: reg18 {
 +                              regulator-name = "reg18";
 +                              regulator-min-microvolt = <1800000>;
 +                              regulator-max-microvolt = <1800000>;
 +                      };
 +
 +                      usb33: usb33 {
 +                              regulator-name = "usb33";
 +                              regulator-min-microvolt = <3300000>;
 +                              regulator-max-microvolt = <3300000>;
 +                      };
 +              };
 +
                exti: interrupt-controller@5000d000 {
-                       compatible = "st,stm32mp13-exti", "syscon";
+                       compatible = "st,stm32mp1-exti", "syscon";
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        reg = <0x5000d000 0x400>;

diff --cc arch/arm/boot/dts/st/stm32mp151.dtsi
index 16bd6eee32b4e24d5b2f1ce99cab743c0b69e2ba,bcb3ed94b265626a88e0e9f221ad45d557c3ed6a..90c5c72c87ab7e7c7ac74b297922f080cb5ab7c1
--- 1/arch/arm/boot/dts/st/stm32mp151.dtsi
--- 2/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@@ -166,70 -227,194 +166,145 @@@
                        };
                };
  
 -              timers5: timer@40003000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-timers";
 -                      reg = <0x40003000 0x400>;
 -                      interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 -                      interrupt-names = "global";
 -                      clocks = <&rcc TIM5_K>;
 -                      clock-names = "int";
 -                      dmas = <&dmamux1 55 0x400 0x1>,
 -                             <&dmamux1 56 0x400 0x1>,
 -                             <&dmamux1 57 0x400 0x1>,
 -                             <&dmamux1 58 0x400 0x1>,
 -                             <&dmamux1 59 0x400 0x1>,
 -                             <&dmamux1 60 0x400 0x1>;
 -                      dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 -                      status = "disabled";
 -
 -                      pwm {
 -                              compatible = "st,stm32-pwm";
 -                              #pwm-cells = <3>;
 -                              status = "disabled";
 -                      };
 -
 -                      timer@4 {
 -                              compatible = "st,stm32h7-timer-trigger";
 -                              reg = <4>;
 -                              status = "disabled";
 -                      };
 -
 -                      counter {
 -                              compatible = "st,stm32-timer-counter";
 -                              status = "disabled";
 -                      };
 +              pwr_mcu: pwr_mcu@50001014 {
 +                      compatible = "st,stm32mp151-pwr-mcu", "syscon";
 +                      reg = <0x50001014 0x4>;
                };
  
 -              timers6: timer@40004000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-timers";
 -                      reg = <0x40004000 0x400>;
 -                      interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 -                      interrupt-names = "global";
 -                      clocks = <&rcc TIM6_K>;
 -                      clock-names = "int";
 -                      dmas = <&dmamux1 69 0x400 0x1>;
 -                      dma-names = "up";
 -                      status = "disabled";
 -
 -                      timer@5 {
 -                              compatible = "st,stm32h7-timer-trigger";
 -                              reg = <5>;
 -                              status = "disabled";
 -                      };
 +              exti: interrupt-controller@5000d000 {
 +                      compatible = "st,stm32mp1-exti", "syscon";
 +                      interrupt-controller;
 +                      #interrupt-cells = <2>;
 +                      reg = <0x5000d000 0x400>;
++                      interrupts-extended =
++                              <&intc GIC_SPI 6   IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_0 */
++                              <&intc GIC_SPI 7   IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 8   IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 9   IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 23  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 64  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 65  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 66  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 67  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 40  IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_10 */
++                              <&intc GIC_SPI 42  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 76  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 77  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <0>,
++                              <&intc GIC_SPI 3   IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,                                            /* EXTI_20 */
++                              <&intc GIC_SPI 31  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 33  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 72  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 95  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 37  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 38  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 39  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 71  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 52  IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_30 */
++                              <&intc GIC_SPI 53  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 82  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 83  IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,                                            /* EXTI_40 */
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 93  IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_50 */
++                              <0>,
++                              <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
++                              <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <0>,                                            /* EXTI_60 */
++                              <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <0>,
++                              <0>,
++                              <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <0>,
++                              <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
++                              <0>,
++                              <&intc GIC_SPI 62  IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_70 */
++                              <0>,
++                              <0>,
++                              <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
                };
  
 -              timers7: timer@40005000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-timers";
 -                      reg = <0x40005000 0x400>;
 -                      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 -                      interrupt-names = "global";
 -                      clocks = <&rcc TIM7_K>;
 -                      clock-names = "int";
 -                      dmas = <&dmamux1 70 0x400 0x1>;
 -                      dma-names = "up";
 -                      status = "disabled";
 -
 -                      timer@6 {
 -                              compatible = "st,stm32h7-timer-trigger";
 -                              reg = <6>;
 -                              status = "disabled";
 -                      };
 +              syscfg: syscon@50020000 {
 +                      compatible = "st,stm32mp157-syscfg", "syscon";
 +                      reg = <0x50020000 0x400>;
 +                      clocks = <&rcc SYSCFG>;
                };
  
 -              timers12: timer@40006000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-timers";
 -                      reg = <0x40006000 0x400>;
 -                      interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 -                      interrupt-names = "global";
 -                      clocks = <&rcc TIM12_K>;
 -                      clock-names = "int";
 +              dts: thermal@50028000 {
 +                      compatible = "st,stm32-thermal";
 +                      reg = <0x50028000 0x100>;
 +                      interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 +                      clocks = <&rcc TMPSENS>;
 +                      clock-names = "pclk";
 +                      #thermal-sensor-cells = <0>;
                        status = "disabled";
 -
 -                      pwm {
 -                              compatible = "st,stm32-pwm";
 -                              #pwm-cells = <3>;
 -                              status = "disabled";
 -                      };
 -
 -                      timer@11 {
 -                              compatible = "st,stm32h7-timer-trigger";
 -                              reg = <11>;
 -                              status = "disabled";
 -                      };
                };
  
 -              timers13: timer@40007000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-timers";
 -                      reg = <0x40007000 0x400>;
 -                      interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 -                      interrupt-names = "global";
 -                      clocks = <&rcc TIM13_K>;
 -                      clock-names = "int";
 -                      status = "disabled";
 -
 -                      pwm {
 -                              compatible = "st,stm32-pwm";
 -                              #pwm-cells = <3>;
 -                              status = "disabled";
 -                      };
 -
 -                      timer@12 {
 -                              compatible = "st,stm32h7-timer-trigger";
 -                              reg = <12>;
 -                              status = "disabled";
 -                      };
 +              mdma1: dma-controller@58000000 {
 +                      compatible = "st,stm32h7-mdma";
 +                      reg = <0x58000000 0x1000>;
 +                      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 +                      clocks = <&rcc MDMA>;
 +                      resets = <&rcc MDMA_R>;
 +                      #dma-cells = <5>;
 +                      dma-channels = <32>;
 +                      dma-requests = <48>;
                };
  
 -              timers14: timer@40008000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-timers";
 -                      reg = <0x40008000 0x400>;
 -                      interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 -                      interrupt-names = "global";
 -                      clocks = <&rcc TIM14_K>;
 -                      clock-names = "int";
 +              sdmmc1: mmc@58005000 {
 +                      compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 +                      arm,primecell-periphid = <0x00253180>;
 +                      reg = <0x58005000 0x1000>;
 +                      interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 +                      clocks = <&rcc SDMMC1_K>;
 +                      clock-names = "apb_pclk";
 +                      resets = <&rcc SDMMC1_R>;
 +                      cap-sd-highspeed;
 +                      cap-mmc-highspeed;
 +                      max-frequency = <120000000>;
                        status = "disabled";
 -
 -                      pwm {
 -                              compatible = "st,stm32-pwm";
 -                              #pwm-cells = <3>;
 -                              status = "disabled";
 -                      };
 -
 -                      timer@13 {
 -                              compatible = "st,stm32h7-timer-trigger";
 -                              reg = <13>;
 -                              status = "disabled";
 -                      };
                };
  
 -              lptimer1: timer@40009000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32-lptimer";
 -                      reg = <0x40009000 0x400>;
 -                      interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 -                      clocks = <&rcc LPTIM1_K>;
 -                      clock-names = "mux";
 -                      wakeup-source;
 -                      status = "disabled";
 -
 -                      pwm {
 -                              compatible = "st,stm32-pwm-lp";
 -                              #pwm-cells = <3>;
 -                              status = "disabled";
 -                      };
 -
 -                      trigger@0 {
 -                              compatible = "st,stm32-lptimer-trigger";
 -                              reg = <0>;
 -                              status = "disabled";
 -                      };
 -
 -                      counter {
 -                              compatible = "st,stm32-lptimer-counter";
 -                              status = "disabled";
 -                      };
 -              };
 -
 -              spi2: spi@4000b000 {
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -                      compatible = "st,stm32h7-spi";
 -                      reg = <0x4000b000 0x400>;
 -                      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 -                      clocks = <&rcc SPI2_K>;
 -                      resets = <&rcc SPI2_R>;
 -                      dmas = <&dmamux1 39 0x400 0x05>,
 -                             <&dmamux1 40 0x400 0x05>;
 -                      dma-names = "rx", "tx";
 +              sdmmc2: mmc@58007000 {
 +                      compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 +                      arm,primecell-periphid = <0x00253180>;
 +                      reg = <0x58007000 0x1000>;
 +                      interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 +                      clocks = <&rcc SDMMC2_K>;
 +                      clock-names = "apb_pclk";
 +                      resets = <&rcc SDMMC2_R>;
 +                      cap-sd-highspeed;
 +                      cap-mmc-highspeed;
 +                      max-frequency = <120000000>;
                        status = "disabled";
                };
  

diff --cc arch/arm64/Kconfig.platforms
Simple merge

diff --cc arch/arm64/boot/dts/st/stm32mp251.dtsi
index 4b48e4ed2d284cc22e50b9d77e0f264cc1fc8da1,e7d1614dc744cf88a0239eeb7e88cf07df453697..dcd0656d67a807d07062d992204c9a1b7d5aa1ce
--- 1/arch/arm64/boot/dts/st/stm32mp251.dtsi
--- 2/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@@ -356,93 -168,99 +356,186 @@@
                        };
                };
  
 +              rcc: clock-controller@44200000 {
 +                      compatible = "st,stm32mp25-rcc";
 +                      reg = <0x44200000 0x10000>;
 +                      #clock-cells = <1>;
 +                      #reset-cells = <1>;
 +                      clocks = <&scmi_clk CK_SCMI_HSE>,
 +                              <&scmi_clk CK_SCMI_HSI>,
 +                              <&scmi_clk CK_SCMI_MSI>,
 +                              <&scmi_clk CK_SCMI_LSE>,
 +                              <&scmi_clk CK_SCMI_LSI>,
 +                              <&scmi_clk CK_SCMI_HSE_DIV2>,
 +                              <&scmi_clk CK_SCMI_ICN_HS_MCU>,
 +                              <&scmi_clk CK_SCMI_ICN_LS_MCU>,
 +                              <&scmi_clk CK_SCMI_ICN_SDMMC>,
 +                              <&scmi_clk CK_SCMI_ICN_DDR>,
 +                              <&scmi_clk CK_SCMI_ICN_DISPLAY>,
 +                              <&scmi_clk CK_SCMI_ICN_HSL>,
 +                              <&scmi_clk CK_SCMI_ICN_NIC>,
 +                              <&scmi_clk CK_SCMI_ICN_VID>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_07>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_08>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_09>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_10>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_11>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_12>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_13>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_14>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_15>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_16>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_17>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_18>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_19>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_20>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_21>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_22>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_23>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_24>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_25>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_26>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_27>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_28>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_29>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_30>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_31>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_32>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_33>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_34>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_35>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_36>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_37>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_38>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_39>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_40>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_41>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_42>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_43>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_44>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_45>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_46>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_47>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_48>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_49>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_50>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_51>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_52>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_53>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_54>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_55>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_56>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_57>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_58>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_59>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_60>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_61>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_62>,
 +                              <&scmi_clk CK_SCMI_FLEXGEN_63>,
 +                              <&scmi_clk CK_SCMI_ICN_APB1>,
 +                              <&scmi_clk CK_SCMI_ICN_APB2>,
 +                              <&scmi_clk CK_SCMI_ICN_APB3>,
 +                              <&scmi_clk CK_SCMI_ICN_APB4>,
 +                              <&scmi_clk CK_SCMI_ICN_APBDBG>,
 +                              <&scmi_clk CK_SCMI_TIMG1>,
 +                              <&scmi_clk CK_SCMI_TIMG2>,
 +                              <&scmi_clk CK_SCMI_PLL3>,
 +                              <&clk_dsi_txbyte>;
 +              };
 +
+               exti1: interrupt-controller@44220000 {
+                       compatible = "st,stm32mp1-exti", "syscon";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       reg = <0x44220000 0x400>;
+                       interrupts-extended =
+                               <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_0 */
+                               <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_10 */
+                               <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,                                            /* EXTI_20 */
+                               <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_30 */
+                               <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,
+                               <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_40 */
+                               <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_50 */
+                               <0>,
+                               <0>,
+                               <0>,
+                               <0>,
+                               <0>,
+                               <0>,
+                               <0>,
+                               <0>,
+                               <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,                                            /* EXTI_60 */
+                               <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,
+                               <0>,
+                               <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,
+                               <0>,
+                               <&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,
+                               <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,        /* EXTI_70 */
+                               <0>,
+                               <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                               <0>,                                            /* EXTI_80 */
+                               <0>,
+                               <0>,
+                               <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+               };
+ 
                syscfg: syscon@44230000 {
                        compatible = "st,stm32mp25-syscfg", "syscon";
                        reg = <0x44230000 0x10000>;

diff --cc drivers/irqchip/irq-gic-v3-its.c
Simple merge

diff --cc kernel/irq/manage.c
Simple merge

diff --cc lib/Kconfig.debug
Simple merge