static inline int xtensa_get_ring(const CPUXtensaState *env)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ if (xtensa_option_bits_enabled(env->config,
+ XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) {
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
} else {
return 0;
static inline int xtensa_get_cring(const CPUXtensaState *env)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
- (env->sregs[PS] & PS_EXCM) == 0) {
+ if (xtensa_option_bits_enabled(env->config,
+ XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) &&
+ (env->sregs[PS] & PS_EXCM) == 0) {
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
} else {
return 0;
uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
PS_UM | PS_EXCM | PS_INTLEVEL;
- if (option_enabled(dc, XTENSA_OPTION_MMU)) {
+ if (option_enabled(dc, XTENSA_OPTION_MMU) ||
+ option_enabled(dc, XTENSA_OPTION_MPU)) {
mask |= PS_RING;
}
tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask);