aarch64: Use 64-bit variable to access the special registers

clang issues:

  error: value size does not match register size specified by the
  constraint and modifier [-Werror,-Wasm-operand-widths]

while tryng to use 32 bit variables with 'mrs' to get/set the
fpsr, dczid_el0, and ctr.

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 5df6da3ffced22c06aa5cddf3712fd907d694076..a93dbf5efaa833699d029f4d1b9ebc4761fd4938 100644 (file)
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs   %0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr   fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs   %0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr   fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)                                      \
+  ({                                                           \
+   __uint64_t __fpcr;                                          \
+   __asm__ __volatile__ ("mrs  %0, fpcr" : "=r" (__fpcr));     \
+   fpcr = __fpcr;                                              \
+  })
+
+# define _FPU_SETCW(fpcr)                                      \
+  ({                                                           \
+   __uint64_t __fpcr = fpcr;                                   \
+   __asm__ __volatile__ ("msr  fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)                                    \
+  ({                                                           \
+   __uint64_t __fpsr;                                          \
+   __asm__ __volatile__ ("mrs  %0, fpsr" : "=r" (__fpsr));     \
+   fpsr = __fpsr;                                              \
+  })
+
+# define _FPU_SETFPSR(fpsr)                                    \
+  ({                                                           \
+   __uint64_t __fpsr = fpsr;                                   \
+   __asm__ __volatile__ ("msr  fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register

diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bf5862a56e16eb7f671ef663dffc010aa0ce23af..518a6eb3210cc8b4b48a526e08bdd1ae1e672780 100644 (file)
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -19,11 +19,12 @@
 #include <fenv.h>
 #include <fpu_control.h>
 #include <float.h>
+#include <stdint.h>
 
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  uint64_t fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;

diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961f8778ade0749a5ed03b89ddb4ed7ad..b41a9462dfae742fef584fa6a0c925b175742f21 100644 (file)
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {                                          \
     const float fp_1e32 = 1.0e32f;                                     \
     const float fp_zero = 0.0;                                         \
     const float fp_one = 1.0;                                          \
-    unsigned fpsr;                                                     \
+    uint64_t fpsr;                                                     \
     if (_fex & FP_EX_INVALID)                                          \
       {                                                                        \
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"                     \

diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 26cf6d4a560050e1a9d4c58e9c92c2d7f8bb6251..7ac228303f2fbd9c085a64378622fc275ec9a977 100644 (file)
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -128,7 +128,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)

diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index c0df3af28c93e346a49ae228386795e241492dcf..eec2453abc86867ca8db87cdf816fda53ecf5976 100644 (file)
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  uint64_t ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux