aarch64: Allow multiple fields for sve_aligned_reglist

Update aarch64_{ins|ext}_sve_aligned_reglist to use constant fields
instead of operand specific data for zero-extension/truncation.

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index bac5dfa6397e421f110ab82e836c94d3c9901a94..c9ffdd2c1a994539e8c4b33e9fc7f140a811453e 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1261,9 +1261,8 @@ aarch64_ins_sve_aligned_reglist (const aarch64_operand *self,
                                 const aarch64_inst *inst ATTRIBUTE_UNUSED,
                                 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  unsigned int num_regs = get_operand_specific_data (self);
   unsigned int val = info->reglist.first_regno;
-  insert_field (self->fields[0], code, val / num_regs, 0);
+  insert_all_fields (self, code, val);
   return true;
 }
 

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 8554cd256a516e27d939e6930550b806ce56ac11..601199a56e4c61a0b0d1725d19962e58b200d332 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1891,8 +1891,7 @@ aarch64_ext_sve_aligned_reglist (const aarch64_operand *self,
                                 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   unsigned int num_regs = get_operand_specific_data (self);
-  unsigned int val = extract_field (self->fields[0], code, 0);
-  info->reglist.first_regno = val * num_regs;
+  info->reglist.first_regno = extract_all_fields (self, code);
   info->reglist.num_regs = num_regs;
   info->reglist.stride = 1;
   return true;

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 18de7676bf179752d6da51656ec9af953a6a8e41..02f29c0401ce4eff5a1d90e245fdd66d88222e82 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -280,15 +280,15 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2, FLD_CONST_0}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4, FLD_CONST_00}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "an SVE vector register"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2, FLD_CONST_0}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4, FLD_CONST_00}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4, FLD_CONST_00}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_1b}, "an SME ZA tile ZA0-ZA1"},
@@ -298,7 +298,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"},
   {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
   {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2}, "a list of SVE predicate registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2, FLD_CONST_0}, "a list of SVE predicate registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "a list of SVE predicate registers"},
   {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
   {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_PNd3}, "an SVE predicate-as-counter register"},

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 29321ca79eb72badf132443d1a78da58d626f401..e080707dd154bc970950043ea247de4e722de419 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -227,6 +227,7 @@ const aarch64_field aarch64_fields[] =
 {
     AARCH64_FIELD_NIL, /* NIL.  */
     AARCH64_FIELD_CONST (0, 1),        /* CONST_0.  */
+    AARCH64_FIELD_CONST (0, 2),        /* CONST_00.  */
     AARCH64_FIELD_CONST (1, 1),        /* CONST_1.  */
     AARCH64_FIELD ( 8, 4), /* CRm: in the system instructions.  */
     AARCH64_FIELD (10, 2), /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>.  */

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 7dbc00f64e49a521f68751fef48f74c8bdf4d00a..af0f0d857c09384aa46c08cce06263d572ad7f43 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -31,6 +31,7 @@ enum aarch64_field_kind
 {
   FLD_NIL,
   FLD_CONST_0,
+  FLD_CONST_00,
   FLD_CONST_1,
   FLD_CRm,
   FLD_CRm_dsb_nxs,

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1e33e51e6e04e35ec7d3bfbaea02603468f1c860..bfa235daa8c657e4c707892bf5cc40ab433a0f97 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -8032,24 +8032,24 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt),          \
       "a list of SVE vector registers")                                        \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx2", 2 << OPD_F_OD_LSB,        \
-      F(FLD_SME_Zdn2), "a list of SVE vector registers")               \
+      F(FLD_SME_Zdn2, FLD_CONST_0), "a list of SVE vector registers")  \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB,        \
-      F(FLD_SME_Zdn4), "a list of SVE vector registers")               \
+      F(FLD_SME_Zdn4, FLD_CONST_00), "a list of SVE vector registers") \
     Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm),                      \
       "an SVE vector register")                                                \
     Y(SVE_REG, regno, "SME_Zm_17", 0, F(FLD_SME_Zm2),                  \
       "an SVE vector register")                                                \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
-      F(FLD_SME_Zm2), "a list of SVE vector registers")                        \
+      F(FLD_SME_Zm2, FLD_CONST_0), "a list of SVE vector registers")   \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
-      F(FLD_SME_Zm4), "a list of SVE vector registers")                        \
+      F(FLD_SME_Zm4, FLD_CONST_00), "a list of SVE vector registers")  \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \
-      F(FLD_SME_Zn2), "a list of SVE vector registers")                        \
+      F(FLD_SME_Zn2, FLD_CONST_0), "a list of SVE vector registers")   \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2_BIT_INDEX",          \
-      2 << OPD_F_OD_LSB, F(FLD_SME_Zn2),                               \
+      2 << OPD_F_OD_LSB, F(FLD_SME_Zn2, FLD_CONST_0),                  \
       "a list of SVE vector registers")                                        \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
-      F(FLD_SME_Zn4), "a list of SVE vector registers")                        \
+      F(FLD_SME_Zn4, FLD_CONST_00), "a list of SVE vector registers")  \
     Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED",            \
       2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3),                  \
       "a list of SVE vector registers")                                        \
@@ -8075,7 +8075,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0),                              \
       "an SME horizontal or vertical vector access register")          \
     Y(SVE_REGLIST, sve_aligned_reglist, "SME_Pdx2", 2 << OPD_F_OD_LSB, \
-      F(FLD_SME_Pdx2), "a list of SVE predicate registers")            \
+      F(FLD_SME_Pdx2, FLD_CONST_0), "a list of SVE predicate registers")\
     Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD_SVE_Pd),          \
       "a list of SVE predicate registers")                             \
     Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm),                     \